Browsing by Author "Bolshakov, Pavel"
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Item Dual-Gate MoS₂ Transistors with Sub-10 NM Top-Gate High-K Dielectrics(American Institute of Physics Inc.) Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Hurley, P. K.; Hinkle, Christopher L.; Wallace, Robert M.; Young, Chadwin D.; 0000-0002-3530-6400 (Zhao, P); 0000-0001-5566-4806 (Wallace, RM); 0000-0003-0690-7423 (Young, CD); Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Hinkle, Christopher L.; Wallace, Robert M.; Young, Chadwin D.High quality sub-10 nm high-k dielectrics are deposited on top of MoS₂ and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO₂ and an Al₂O₃/HfO₂ bilayer shows significant improvement in device performance due to the insertion of the thin Al₂O₃ layer. The results show that the Al₂O₃ buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS₂/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al₂O₃ dielectric demonstrate a near-ideal subthreshold swing of ~60 mV/dec and a high field effect mobility of 100 cm²/V·s.Item Engineering The Palladium-WSe₂ Interface Chemistry for Field Effect Transistors with High-Performance Hole Contacts(Amer Chemical Soc, 2018-12-07) Smyth, Christopher M.; Walsh, Lee A.; Bolshakov, Pavel; Catalano, Massimo; Addou, Rafik; Wang, Luhua; Kim, Jiyoung; Kim, Moon J.; Young, Chadwin D.; Hinkle, Christopher L.; Wallace, Robert M.; 0000-0001-5566-4806 (Wallace, RM); 0000-0003-0690-7423 (Young, CD); 0000-0003-2781-5149 (Kim, J); 0000-0002-6688-8626 (Walsh, LA); 0000-0002-5485-6600 (Hinkle, CD); 0000-0002-5454-0315 (Addou, R); 70133685 (Kim, J); Smyth, Christopher M.; Walsh, Lee A.; Bolshakov, Pavel; Catalano, Massimo; Addou, Rafik; Wang, Luhua; Kim, Jiyoung; Kim, Moon J.; Young, Chadwin D.; Hinkle, Christopher L.; Wallace, Robert M.Palladium has been widely employed as a hole contact to WSe₂ and has enabled, at times, the highest WSe₂ transistor performance. However, there are orders of magnitude variation across the literature in Pd-WSe₂ contact resistance and I-ON/I-OFF ratios with no true understanding of how to consistently achieve high-performance contacts. In this work, WSe₂ transistors with impressive I-ON/I-OFF ratios of 10(6) and Pd-WSe₂ Schottky diodes with near-zero variability are demonstrated utilizing Ohmic-like Pd contacts through deliberate control of the interface chemistry. The increased concentration of a PdSeₓ intermetallic is correlated with an Ohmic band alignment and concomitant defect passivation, which further reduces the contact resistance, variability, and barrier height inhomogeneity. The lowest contact resistance occurs when a 60 min post-metallization anneal at 400 degrees C in forming gas (FG) is performed. X-ray photoelectron spectroscopy indicates this FG anneal produces 3x the concentration of PdSeₓ and an Ohmic band alignment, in contrast to that detected after annealing in ultrahigh vacuum, during which a 0.2 eV hole Schottky barrier forms. Raman spectroscopy and scanning transmission electron microscopy highlight the necessity of the fabrication step to achieve high-performance contacts as no PdSeₓ forms, and WSe₂ is unperturbed by room temperature Pd deposition. However, at least one WSe₂ layer is consumed by the necessary interface reactions that form PdSeₓ requiring strategic exploitation of a sacrificial WSe₂ layer during device fabrication. The interface chemistry and structural properties are correlated with Pd-WSe₂ diode and transistor performance, and the recommended processing steps are provided to enable reliable high-performance contact formation.Item Investigation of Critical Interfaces of Transition Metal Dichalcogenide Devices for Future Device Applications(2019-11-18) Bolshakov, Pavel; Young, Chadwin D.Recently, transition metal dichalcogenides (TMDs) have drawn significant attention due to their two-dimensional structure and unique properties that show the potential for applications in various devices such as transistors, solar cells, and sensors. Initial TMD devices have demonstrated promising results in terms of device performance. However, the high contact resistance and Fermi level pinning at the contact metal – TMD interface prevents efficient carrier injection in electronic devices. Furthermore, the interactions at the bottom-gate high-κ dielectric – TMD interface and at the top-gate high-κ dielectric – TMD interface have not been sufficiently studied using I-V analysis. In this dissertation, device fabrication, physical and electrical characterization, and enhanced device analysis of dual-gate MoS2 field-effect-transistors are demonstrated with a focus on the critical interfaces. Bottom-gate MoS2 transistors and capacitors with high-κ dielectrics are characterized using I-V and C-V measurements to determine the influence of the bottom-gate dielectric on top-gate transistor performance. Electrical characterization through the dual-gate transistor fabrication process is done to determine the type of charge HfO2 introduces on the top MoS2 surface compared to Al2O3/HfO2 bilayer. Dual-gate sweeping methodology is introduced to TMD transistors in order to understand the influence of the top-gate dielectric compared to the bottom-gate dielectric on device performance. An oxygen plasma clean is used during device contact patterning to functionalize the MoS2 surface to de-pin the Fermi level and allow for low contact resistance formation. Low contact resistance combined with high quality high-κ dielectric gate stacks in conjunction with dual-gate sweeping is studied. Devices with sub-thermionic transport are observed and enhanced I-V analysis and modeling is done to determine the potential origins of the sub-60 mV/dec phenomenon. The electrical and physical characterization and analysis of critical interfaces of TMD devices in this dissertation provides insights into the interfacial influence on device performance and the origins of any defects present.Item Positive Bias Instability in ZnO TFTs with Al₂O₃ Gate Dielectric(Institute of Electrical and Electronics Engineers Inc., 2019-03-31) Bolshakov, Pavel; Rodriguez-Davila, Rodolfo A.; Quevedo-López, Manuel A.; Young, Chadwin D.; 0000-0003-0690-7423 (Young, CD); Bolshakov, Pavel; Rodriguez-Davila, Rodolfo A.; Quevedo-López, Manuel A.; Young, Chadwin D.Positive bias instability stress (PBI) was done on ZnO thin-film transistors (TFTs) with Al₂O₃ deposition at 100°C and 250°C. The threshold voltage (VT), transconductance (g ₘ), and subthreshold slope (SS) were monitored where the 100°C samples demonstrated a 'turn-around' phenomenon in the ΔVₜ compared to the 250°C samples. The 250°C samples show consistent ΔVₜ, suggesting a higher Al₂O₃ deposition temperature results in the absence of the defect responsible for the 'turn-around' effect. Both sets also demonstrate negligible degradation in Δgₘ and ASS -suggesting little to no influence on the Vₜ shift by interfacial state generation. © 2019 IEEE.Item Sensitivity of High-k Encapsulated MoS₂ Transistors to I-V Measurement Execution Time(Institute of Electrical and Electronics Engineers Inc.) Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Wallace, Robert M.; Young, Chadwin D.; Hurley, P. K.; Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Wallace, Robert M.; Young, Chadwin D.High-k encapsulated MoS₂ field-effect-transistors were fabricated and electrically characterized. Comparison between HfO₂ and Al₂O₃ encapsulated MoS₂ FETs and their I-V response to execution time are shown. Changes in gate voltage step and integration time demonstrate that electrical characterization parameters can significantly impact device parameters such as the subthreshold swing and the threshold voltage. © 2018 IEEE.