Browsing by Author "Neethirajan, Deepika"
Now showing 1 - 2 of 2
- Results Per Page
- Sort Options
Item Machine Learning-based Solutions for Comprehending and Mitigating Imperfections of Semiconductor Manufacturing and Testing(2022-12-01T06:00:00.000Z) Neethirajan, Deepika; Makris, Yiorgos; Rodrigues, Danieli; Henderson, Rashaunda; Nourani, Mehrdad; Friedman, JosephIn recent years, significant technological advancements have been made in the semiconductor industry; However, with these advancements, comes a lot of manufacturing and testing challenges that have a direct impact on the cost and yield of the overall outcome. While advanced technology nodes enable production of more powerful devices that have a smaller form factor, operation of such devices is more susceptible to process variations. To address the impacts of process variations without impacting the performance of devices, manufacturers employ post-silicon calibration techniques. One major pitfall of post-silicon calibration is the need to perform numerous test measurements and adjustments that significantly contribute towards the overall test time, thereby hindering the profit margins of new products. Along with the minimal cost expectations, there are higher quality expectations in terms of extremely low number of defects. This results in implementing exhaustive and contemporary test solutions that result in a non-negligible amount of good devices being discarded. In this work, several machine learning-based solutions are proposed to address the increasing test costs and to recover some of the yield loss. An adaptive test cost reduction technique is proposed to identify the optimal operating voltage for a High-Volume Manufacturing (HVM) device, by taking advantage of the correlation that exists between different test measurements and operating voltages. Another test cost reduction technique was proposed to enable testing a device across multiple temperature corners, where the current testing process is extremely time consuming and expensive. Towards addressing the problem of impairments that affect the performance of Radio Frequency (RF) transmitters due to process variations, a machine- learning based solution was proposed to classify and decompose the RF impairments. The model leverages unique signatures left by the impairments on the transmitted signal constellation points. Towards recovering yield loss caused by using conservative test programs that help achieve higher quality expectations, a machine learning based solution was proposed, which exploits the statistical correlation between two key groups of tests currently performed for these devices. Finally, to avoid die damage that occurs due to misalignment of the blades used in the wafer dicing equipment, a machine learning-based solution was proposed that takes advantage of the acoustic emissions recorded by the dicing equipment. All the proposed solutions have been evaluated using dataset provided by our industry liaisons and the results are shown in this work.Item Wafer-Level Adaptive Vₘᵢₙ Calibration Seed Forecasting(Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Xanthopoulos, Constantinos; Neethirajan, Deepika; Boddikurapati, S.; Nahar, A.; Makris, Yiorgos; Xanthopoulos, Constantinos; Neethirajan, Deepika; Makris, YiorgosTo combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vₘᵢₙ) of a given Integrated Circuit. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vₘᵢₙ calibration search, by identifying the optimal wafer-level search parameters. The effectiveness of the proposed methodology is demonstrated on an industrial dataset. © 2019 EDAA.