Browsing by Author "Tian, Jingxiang"
Now showing 1 - 2 of 2
- Results Per Page
- Sort Options
Item Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming(Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, Yiorgos; 110195631 (Sechen, CM); Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, YiorgosWidespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, concerted interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction and usage of ICs has surfaced. To this end, in this paper we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication TRAnsistor-level Programming (TRAP). We introduce a transistor-level programmable fabric and we discuss its unique advantages towards design obfuscation, as well as a customized CAD framework for seamlessly integrating this fabric in an ASIC design flow. We theoretically analyze the complexity of attacking TRAP-obfuscated designs through both brute-force and intelligent SAT-based attacks and we present a silicon implementation of a platform for experimenting with TRAP. Effectiveness of the proposed method is evaluated through selective obfuscation of various modules of a modern microprocessor design. Results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks, while incurring an order of magnitude less area, power and delay overhead. © 2019 EDAA.Item Transistor-Level Programmable Fabric(2019-12) Tian, Jingxiang; Sechen, Carl; Makris, YiorgosWe introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. This TRAnsistor-level Programmable (TRAP) fabric allows simultaneous storage of four independent configurations, along with the ability to dynamically switch between them in a small fraction of a clock cycle. We term this board-level virtualization in that each configuration, in effect, implements an independent chip. TRAP also supports chip-level virtualization in which a single IC design is partitioned over a set of configurations and the computation cycles from one configuration to the next in the set. This allows a design that requires more computational logic than physically available on the TRAP chip to be nonetheless executable. TRAP also features rapid partial or full modification of any one of the stored configurations in a time proportional to the number of modified configuration bits through the use of hierarchically arranged, high throughput, pipelined memory buffers. TRAP supports libraries of cells of the same height and variable width, just as in a typical standard cell circuit. We developed a complete Computer-aided Design (CAD) tool flow for programming TRAP chips. A prototype 3mm X 3mm TRAP chip was fabricated using the Global Foundries 55nm process. We show that TRAP has substantially better area efficiency compared to a leading industrial FPGA and would, therefore, be ideal for embedded FPGA (eFPGA) applications.