Browsing by Author "Xanthopoulos, Konstantinos"
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Item Applications of Machine Learning in Test Cost Reduction and Quality Improvement(2019-12) Xanthopoulos, Konstantinos; Makris, YiorgosThe production of Integrated Circuits (ICs) is one of the most intricate processes currently performed in the world on such a large scale. Due to this complexity, process variations that are present in any manufacturing field, are intensified, resulting in compromising the main production goals, performance, reliability, and low cost. To combat the effects of process variations, multiple control steps have been introduced in the process at all stages, to test, filter, or re-calibrate the material produced. Despite considerable efforts to simultaneously attain all three goals of manufacturing, such solutions have not yet been established. Instead, depending on the product goals, only two of the goals are targeted, consequently compromising the third. In this work, we aim to study solutions where performance, reliability, and low cost can be reached simultaneously. To achieve this, we plan to utilize the plethora of data produced in all stages of the manufacturing process and at many granularity levels, allowing us to design adaptive machine learning-based solutions that counter the effects process variation has in the end result. Several studies will be presented, focusing on cost reduction for testing, which constitutes one of the major cost-bloating factors, and on improving the quality of tests performed. Each study is based on data provided by our industrial collaborators, thus supporting the practicality of the proposed solutions.Item IC Laser Trimming Speed-up Through Wafer-Level Spatial Correlation Modeling(2019-12) Xanthopoulos, Konstantinos; Makris, YiorgosLaser trimming is used extensively to ensure accurate values of on-chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed-loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed-loop control and speeding up the process. Predictions are obtained from wafer-level spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of lasertrimmed ICs.