Zhou, Dian

Permanent URI for this collectionhttps://hdl.handle.net/10735.1/6680

Dian Zhou joined the UT Dallas faculty in 1999 as a full professor in the Department of Electrical Engineering. His research interests include:

  • High Speed and Low Power VLSI Circuits
  • SoCs
  • Analog IC Performance Optimization
  • Silicon Biosensors
  • CAD Tools and Algorithms
  • Biomedical Electronics

Browse

Browsing Zhou, Dian by Subject "Accelerated life testing"

Now showing 1 - 1 of 1
  • Thumbnail Image
    Item
    An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3D ICs
    (Institute of Electrical and Electronics Engineers Inc.) Zhou, H.; Zhu, H.; Cui, T.; Pan, D. Z.; Zhou, D.; Zeng, X.
    Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time consuming for the drop test simulation, therefore, the fast numerical approach is generally needed to reduce the computational cost. In this paper, we propose an efficient drop-test simulator for through-siliconvia (TSV) based three-dimensional integrated circuit (3D IC) to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. And second, an equivalent structureembedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop-test simulator can achieve 7.03× speedup in comparison with the conventional FEM-based solver. It is demonstrated in the paper in the paper through several examples with multi chip layers, of which each chip layer consists of an 8 × 8 TSV array, that the proposed simulator can be widely applied to reliability analysis of 3D ICs under drop impact.

Works in Treasures @ UT Dallas are made available exclusively for educational purposes such as research or instruction. Literary rights, including copyright for published works held by the creator(s) or their heirs, or other third parties may apply. All rights are reserved unless otherwise indicated by the copyright owner(s).