Ma, Dongsheng (Brian)
Permanent URI for this collectionhttps://hdl.handle.net/10735.1/2899
Professor Ma holds the Erik Jonsson Distinguished Chair and is head of the Integrated System Design Laboratory (ISDL), which focuses on developing core technologies for high-performance and low-power integrated systems. The applications range from power management ICs, high-speed high-resolution wire and wireless communication circuits and systems, sensor nodes and networks, to biomedical instruments. In 2017 he was awarded the Distinguished Chair in Microelectronics.
Learn more about Dr. Ma's research on his Profile and Research Explorer pages.
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Item A 25-MHz Four-Phase SAW Hysteretic Control DC-DC Converter with 1-Cycle Active Phase Count(Institute of Electrical and Electronics Engineers Inc., 2019-02-22) Lee, Bumkil; Song, Min Kyu; Maity, Ahsis; Ma, Dongsheng (Brian); 0000-0002-4457-7157 (Ma, DB); Lee, Bumkil; Song, Min Kyu; Maity, Ahsis; Ma, Dongsheng (Brian)In order to meet stringent power requirements in modern application processors, a 25-MHz four-phase dc-dc power converter is presented. It employs an adaptive window hysteretic control to facilitate ultra-fast transient response and minimize output voltage (VO) undershoot and overshoot during load transient periods. Inherent clock synchronization ability ensures current balancing between phase sub-converters. The control also enables a wide range of programmable VO for dynamic voltage/frequency scaling. To maintain high efficiency over a wide power range without degrading transient speed, a 1-cycle active phase count scheme is introduced. A design prototype was fabricated in a 0.35-μm CMOS process with an active die of 1.88 mm2. Simple circuit structure benefits a power density of 3.98 W/mm2. At a switching frequency of 25 MHz and a nominal input of 3.3 V, it regulates a programmable VO ranging from 0.3 to 2.5 V. It achieves more than 80% efficiency over 96.7% of power range with a peak value of 88.1%. In response to 4-A load step-up/down, it achieves 103 mV/123 mV VO undershoot/overshoot with 1% settling time of 190 ns/237 ns, respectively. ©2019 IEEE.Item 15.6 A 10MHz i-Collapse Failure Self-Prognostic GaN Power Converter with TJ -Independent In-Situ Condition Monitoring and Proactive Temperature Frequency Scaling(Institute of Electrical and Electronics Engineers Inc.) Chen, Yingping; Ma, Dongsheng (Brian); Chen, Yingping; Ma, Dongsheng (Brian)With superior figure of merits, GaN switchs are highly anticipated to replace MOSFETs in high-performance power circuits [1], [2]. However, GaN technology today still faces formidable reliability challenges [3]. While GaN device aging and failure mechanisms are not as well-studied as silicon counterparts, its unique structure and operation also induce new aging and failure problems. Use a GaN switch M_H in a buck converter of Fig. 15.6.1 as an example. As a high-side switch, it faces large-switching-current and high-input-voltage stress in each charge phase. After repetitive switching actions, a number of electron carriers can be injected into the AlGaN barrier and buffer layers, known as hot-electron injection. In discharge phase, M_H is off, but M_L becomes conductive, which shorts the source of M_H to ground, creating high VDS stress on M_H. This induces charge traps in the insulator and buffer layers, known as charge trapping. As a joint effect of both mechanisms, trapped or injected electrons in the insulator, AlGaN barrier and buffer layers repel free electrons in the channel when M_H is on, weakening the 2-dimensional electron-gas (2DEG) layer and further elevating hot-electron injection. This effect, known as current collapse or i- collapse for short, degrades channel conductivity, increases the on-resistance RDS_ON, and is a major cause of GaN-switch aging and failure [3]. On the other hand, another aging cause is thermal effect. To reduce manufacture costs and improve technology compatibility, it is common to fabricate GaN transistors on a silicon substrate. Accordingly, to reduce lattice mismatch, an AlGaN buffer layer is often inserted (Fig. 15.6.1). However, this increases the junction-to-ambient thermal resistance R θJA, which, together with the increased R_{DS_ON} due to the i- collapse, causes higher power and heat generation, elevating the junction temperature, T J. According to Arrhenius' Law, as T J increases, the mean-time-to-failure (MTTF) drops exponentially [4]. Even worse, the elevated T_J deteriorates the i- collapse effect with even higher R_{DS_ON}, significantly reducing device lifetime. ©2019 IEEE.Item 15.7 An 8.3MHz GaN Power Converter Using Markov Continuous RSSM for 35dBμV Conducted EMI Attenuation and One-Cycle TON Rebalancing for 27.6dB VO Jittering Suppression(Institute of Electrical and Electronics Engineers Inc.) Chen, Yingping; Ma, Dongsheng (Brian); Chen, Yingping; Ma, Dongsheng (Brian)GaN power switches have gained fast-growing popularity in power electronics. With a similar R DS_ON resistance, they boast 2-to-3-order lower gate capacitance than silicon counterparts, making them highly desirable in high-frequency (fsw ), high-performance power converters. However, at high f sw , switching transitions have to be completed in much shorter times, creating much larger di/dt and dv/dt changes in power stage, which directly link to electromagnetic-interference (EMI) emissions [1]. To suppress EMI, spread-spectrum-modulation (SSM) techniques [2-5] have been proposed. As depicted in Fig. 15.7.1, a periodic SSM (PSSM) is straightforward and easy to implement. However, its EMI suppression is not effective [2]. A randomized SSM (RSSM) can outperform the PSSM, with lower peak EMI and near-uniform noise spreading, but its performance highly relies on the random clock design. In [3], an N-bit digital random clock was reported to achieve a discrete RSSM (D-RSSM). However, the bit number N has to be large in order to achieve satisfying EMI attenuation, significantly increasing circuit complexity, chip area, and power consumption. To overcome this, a thermal-noise-based random clock was proposed [4]. Unfortunately, thermal noise is very sensitive to temperature and is hard to predict. To apply this approach to a practical implementation requires additional signal processing with periodic signals to confine its range of randomization, which, in turn, reduces the benefits of the RSSM. To achieve a near ideal RSSM, a continuous RSSM (C-RSSM) with a cost-effective implementation is highly preferable. Meanwhile, another challenge of applying SSM schemes lies in the fact that the schemes deteriorate V O voltage regulation. As shown in Fig. 15.7.1, as an SSM scheme continuously or periodically modulates f sw , a converter switching period fluctuates cycle by cycle, causing random errors on the duty ratio and thus jittering effect on V O. This is difficult to correct by a feedback control loop, as the duty-ratio error changes randomly between switching cycles. Due to a limited loop-gain bandwidth, the loop response usually lags far behind. Although a ramp compensation scheme was reported to resolve this [5], the improvement is very limited, and the scheme only works for voltage-mode converters. © 2019 IEEE.Item Recent Design Development in Molecular Imaging for Breast Cancer Detection using Nanometer CMOS Based SensorsNguyen, D. C.; Ma, Dongsheng Brian; Roveda, J. M. W.As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8 db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers. © 2012 Dung C. Nguyen et al.