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dc.contributor.authorYoung, Chadwin D.en_US
dc.contributor.authorNeugroschel, Arnosten_US
dc.contributor.authorMajumdar, Kausiken_US
dc.contributor.authorMatthews, Kenen_US
dc.contributor.authorWang, Zheen_US
dc.contributor.authorHobbs, Chrisen_US
dc.date.accessioned2015-03-30T20:56:00Z
dc.date.available2015-03-30T20:56:00Z
dc.date.created2015-01-15
dc.identifier.citationYoung, Chadwin D., Arnost Neugroschel, Kausik Majumdar, Ken Matthews, et al. 2015. "Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors." Journal of Applied Physics 117(3): doi:10.1063/1.4905415.en_US
dc.identifier.issn0021-8979en_US
dc.identifier.urihttp://hdl.handle.net/10735.1/4401
dc.description.abstractThe fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation. The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs.en_US
dc.relation.urihttp://dx.doi.org/10.1063/1.4905415en_US
dc.rights©2015 AIP Publishing LLCen_US
dc.subjectFinFETen_US
dc.subjectCharge coupled devicesen_US
dc.subjectElectric fieldsen_US
dc.subjectDielectricsen_US
dc.subjectNegative bias temperature instability (NBTI)en_US
dc.titleInvestigation of Negative Bias Temperature Instability Dependence on Fin Width of Silicon-On-Insulator-Fin-Based Field Effect Transistorsen_US
dc.type.genrearticleen_US
dc.source.journalJournal of Applied Physicsen_US
dc.identifier.volume117en_US
dc.identifier.issue3en_US
dc.contributor.utdAuthorYoung, Chadwin D.
dc.contributor.utdAuthorNeugroschel, Arnost
dc.contributor.utdAuthorMajumdar, Kausik
dc.contributor.utdAuthorMatthews, Ken
dc.contributor.utdAuthorWang, Zhe
dc.contributor.utdAuthorHobbs, Chris


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