Comprehensive Capacitance-Voltage Analysis Including Quantum Effects for High-K Interfaces on Germanium and Other Alternative Channel Materials
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High mobility alternative channel materials to silicon are critical to the continued scaling of metal oxide semiconductor (MOS) devices. However, before they can be incorporated into advanced devices, some major issues need to be solved. The high mobility materials suffer from lower allowable thermal budgets compared to Si (before desorption and defect formation becomes an issue) and the absence of a good quality native oxide has further increased the interest in the use of high-k dielectrics. However, the high interface state density and high electric fields at these semiconductor/high-k interfaces can significantly impact the capacitance-voltage (C-V) profile, and current C-V modeling software cannot account for these effects. This in turn affects the parameters extracted from the C-V data of the high mobility semiconductor/high-k interface, which are crucial to fully understand the interface properties and expedite process development. To address this issue, we developed a model which takes into account quantum corrections which can be applied to a number of these alternative channel materials including SixGe1−x, Ge, InGaAs, and GaAs. The C-V simulation using this QM correction model is orders of magnitude faster compared to a full band Schrodinger-Poisson solver. The simulated C-V is directly benchmarked to a self consistent Schrodinger-Poisson solution for each bulk semiconductor material, and from the benchmarking process the QM correction parameters are extracted. The full program, C-V Alternative Channel Extraction (CV ACE), incorporates a quantum mechanical correction model, along with the interface state density model, and can extract device parameters such as equivalent oxide thickness (EOT), doping density and flat band voltage (Vfb) as well as the interface state density profile using multiple measurements performed at different frequencies and temperatures, simultaneously. The program was used to analyze experimentally measured C-V profiles and the extracted device parameters show excellent agreement with the known device structure and previously published results. CV ACE has been applied in the development of a process flow for germanium interface passivation in Ge based MOS devices using a GeOx interlayer. A post atomic layer deposition (ALD) plasma oxidation (PPO) process was developed using radio frequency (RF) plasma in a plasma enhanced chemical vapor deposition (PECVD) chamber and demonstrated significant surface passivation. Various gases were investigated and 1% O2/Ar was found to reduce the growth rate and provide excellent control over the degradation of EOT. A 100 W plasma with 1% O2/Ar was found to provide the best combination of EOT and low Dit and is concluded to be the optimum process for PPO of germanium surfaces. CV ACE and PPO were also utilized to investigate other process development challenges. A study of the impact of low temperature anneals on Ge-based MOS devices was found to result in a degradation of the electrical thickness and a change in fixed charge, indicating that the process window is very narrow and at much lower temperatures than for Si.