The Graphene Field Effect Transistor: A Large Scale Integration Approach

Abstract

Owing to the continuous down scaling of devices as per Moore’s law and the simultaneous need to increase the processing efficiency of the transistor, graphene was found to be the potential candidate for the post silicon electronics due to its predicted theoretical mobility of 200,000 cm2/V. s and one atom thickness. However, due to its semi metallic nature with no bandgap and a linear electronic dispersion structure, the use of graphene field effect transistors in logic circuits is not feasible as there is no off state and the on to off ratio is lesser than the required criteria of 104. Nevertheless, its usability in radio frequency applications is still significant because of the higher cut-off frequency and the predicted ability to saturate the mobility at higher electric fields. Mechanically exfoliated, epitaxially grown graphene has limitations in terms of reproducibility and scalability. CVD graphene is a viable source for fabricating transistors on a large scale. Different processes developed with the objective of making consistent and reliable graphene field effect transistors, packaging them for practical applications are discussed in this thesis.