Calibration Techniques for High Speed Time-Interleaved SAR ADC

Abstract

The emerging applications such as Internet-of-Things (IoT), self-driven car and artificial intelligence (AI) trigger rapid increase in bandwidth demand in data centers and telecommunication infrastructure. The data traffic in global network is expected to be tripled by 2020 and the ITRS predicts the IO speed to exceed 60GB/s in 2020. ADC-based backplane receivers and coherent fiber-optical receivers are promising technologies for the next generation wireline communication systems. For both technologies, high speed analog-to-digital converter (ADC) of over 20GS/s is one key enabler. For 5G wireless communication system high resolution ADC (12bit) with sampling speed over 1GHz is required. Many other application also demands ADC with performance that has never been achieved before while only provides a strict power budget.

Time-interleaving massive slow-but-efficient subADCs to achieve the target is one practical way. However, the benefit brought by time-interleaving is not free. Mismatch between subADCs often limits its linearity making the performance of the array far from the individual subADCs. Among all different kinds of mismatches, dynamic mismatch including skew and bandwidth mismatch are the hardest to identify and cure. This dissertation will introduce two different methods to calibrate the skew mismatch of TI-ADC. Two fabricated chip 12b 1GS/s and 6b 24GS/s will be shown as the silicon verification of the proposed methods.