Efficient and Quality Assured Techniques for Analog Circuit Design Automation

Automating the designs of analog and mixed signal circuits is challenging because circuit designs are heuristics intensive and the performance evaluations are expensive. This dissertation addresses multiple strategies to enhance the quality and efficiency of the circuit design automation. With comparing various global optimization solvers such as Evolutionary Algorithm (EA), Simulated Annealing (SA) and Genetic Algorithms (GA), we introduce Random Region Covering (RRC) method as our global optimizer. RRC explores the landscape by initiating local optimization solvers with multiple random starting points. The optimization quality improves as the number of starting points increases. We propose Random Region Covering Theory (RRCT) theory to explain why this technique is efficient at searching for the global optimum. In addition to analyzing the efficiency of the RRC, the theory gives a probability-based estimation of the goodness of the optimization result. Quantifying the goodness of the current design has two advantages. First, we can estimate the improvement margin of the candidate design. In this case, we can avoid extra costs associated with over-optimizing a qualified design. Second, we can estimate the cost of achieving the design goal which provides a sound termination condition to the optimization flow. To enhance the efficiency, an optimization scheme should either speed up the circuit simulation or invoke the high-cost circuit simulator as little as possible. A common technique to improve circuit simulation efficiency is to replace the transistor level model with a behavior level model. However, the accuracy of equation-based or knowledge-based behavioral models is problem dependent. For new circuit topologies, these methods have to develop fitted mathematical models which are time consuming and difficult, particularly with respect to Process, Voltage and Temperature (PVT) variations. Instead of directly applying a numerical optimization algorithm to full transistor-level response surface, it is more efficient to apply the optimization to a surrogate model trained by an iteratively updated, high-fidelity simulation database. The accuracy of the surrogate model becomes the key to achieving high quality optimization results. This dissertation proposes a novel optimization scheme with combining the advantages of Gaussian process (GP) model with RRC optimizer. We perform experiments to compare the proposed technique with well-known Bayesian Optimization (BO) methods. The results proved the effectiveness of the proposed method. The DesignEasy software was developed to implement the above functions and to provide a general User Interface (UI) for circuit design automation.