Time-Domain Analog-to-Digital Conversion and Gigahertz Time-Domain Folding/Flash ADC
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High-speed ADCs with 6~10-bit resolution and multi-gigahertz sampling rate are highly demanded in next generation wireless and wireline communication systems. For the wireline communication systems, such as backplane receivers and 10GBASE-T, 10+ GS/s, 6-8b ADCs are under great demand to deliver higher bit rate with PAM-4 modulation. In this work, a 10 GS/s 6 bit time domain (TD) folding ADC with single voltage-to-time converter (VTC) front-end eliminates the clock skew problem in time-interleaving (TI) architecture. Inherent dynamic element matching (DEM) also ensures good linearity. The RO-based folding time-to-digital converter (TDC) achieves high area efficiency too. This chip achieves a good SFDR of 42 dB with the minimum chip area among state-of-art counterparts. In modern RADAR systems and 5G base stations, high speed ADCs with high input bandwidth enables RF sampling, which can significantly reduce the RF frontend complexity. This work proposed a 2 GS/s 8 bit Flash ADC based on novel TD remainder number system (RNS). The RNS architecture significantly reduces the CMP numbers of a Flash ADC, leading to low complexity and power consumption. An effective resolution bandwidth (ERBW) of 1.74 GHz is achieved with the low input capacitance enabled by the TD approach. This work achieves a higher sampling rate/ERBW while consuming lower power than conventional Flash ADCs, which shows great potential in future RADAR systems.