A 0.1 PS Resolution Coarse-Fine Time-To-Digital Converter with 2.21 PS Single-Shot Precision

This dissertation proposes a new type of time-to-digital converter based on a resistor-capacitor (RC) delay line that offers low power consumption, high speed and high resolution with error-correction circuitry. The 14-bit, 0.1 picosecond resolution interpolating coarse-fine time-to-digital converter (TDC) has been developed in 45 nm complementary metal–oxide–semiconductor (CMOS) technology. It is based on an asynchronous buffer delay line and an RC delay line. A lookup-table (LUT) based calibration scheme was developed to correct non-linearities due to process, voltage and temperature (PVT) variations. The root mean square (rms) single-shot precision of the TDC is 4.18 picosecond (ps) without the LUT but is 2.21 ps with the LUT. The power consumption is 2.05 mW at 500 MHz with a 1.3 V operating supply voltage. Compared to other high-resolution state-of-the-art TDCs, the proposed TDC achieves the best figure-of-merit (FOM) of 0.723 fJ per conversion step.