• Login
    View Item 
    •   Treasures Home
    • Academic Schools and Programs
    • Erik Jonsson School of Engineering and Computer Science
    • JECS Faculty Research
    • Fischetti, Massimo V.
    • View Item
    •   Treasures Home
    • Academic Schools and Programs
    • Erik Jonsson School of Engineering and Computer Science
    • JECS Faculty Research
    • Fischetti, Massimo V.
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Theoretical Simulation of Negative Differential Transconductance in Lateral Quantum Well nMOS Devices

    Thumbnail
    View/Open
    Article (1.644Mb)
    Date
    2017-01-23
    Author
    Vyas, P. B.
    Naquin, C.
    Edwards, H.
    Lee, Mark
    Vandenberghe, W. G.
    Fischetti, Massimo V.
    Metadata
    Show full item record
    Abstract
    Abstract
    We present a theoretical study of the negative differential transconductance (NDT) recently observed in the lateral-quantum-well Si n-channel field-effect transistors J. Appl. Phys. 118, 124505 (2015)]. In these devices, p⁺ doping extensions are introduced at the source-channel and drain-channel junctions, thus creating two potential barriers that define the quantum well across whose quasi-bound states resonant/sequential tunneling may occur. Our study, based on the quantum transmitting boundary method, predicts the presence of a sharp NDT in devices with a nominal gate length of 10-to-20 nm at low temperatures (~10 K). At higher temperatures, the NDT weakens and disappears altogether as a result of increasing thermionic emission over the p⁺ potential barriers. In larger devices (with a gate length of 30 nm or longer), the NDT cannot be observed because of the low transmission probability and small energetic spacing (smaller than k_{B}T) of the quasi-bound states in the quantum well. We speculate that the inability of the model to predict the NDT observed in 40 nm gate-length devices may be due to an insufficiently accurate knowledge of the actual doping profiles. On the other hand, our study shows that NDT suitable for novel logic applications may be obtained at room temperature in devices of the current or near-future generation (sub-10 nm node), provided an optimal design can be found that minimizes the thermionic emission (requiring high p⁺ potential-barriers) and punch-through (that meets the opposite requirement of potential-barriers low enough to favor the tunneling current).
    URI
    http://hdl.handle.net/10735.1/6100
    Collections
    • Fischetti, Massimo V.
    • Lee, Mark
    • Vandenberghe, William G.

    DSpace software copyright © 2002-2016  DuraSpace
    Contact Us | Send Feedback
    Theme by 
    Atmire NV
     

     

    Browse

    All of TreasuresCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

    My Account

    Login

    DSpace software copyright © 2002-2016  DuraSpace
    Contact Us | Send Feedback
    Theme by 
    Atmire NV