Automating FPGA-based Hardware Acceleration
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In the field of field programmable gate array (FPGA), High-level synthesis (HLS) has shown to be a valid contender to traditional RT-Level based VLSI design based on low-level hardware Description Languages (HDLs) such as Verilog or VHDL. HLS facilitates hardware (HW) engineers do use FPGAs using high-level language, such as C / C ++ / System, by converting these automatically into efficient HDLs. Furthermore, HLS helps to reduce the development process time. In addition, HLS opens a door to software (SW) engineers and beginner HW engineers to the use of FPGA. However, HLS is still not a magic bullet and requires substantial HW knowledge to generate optimized circuits and more important to have a final working FPGA prototype. This thesis aims at facilitating the use of FPGA to non-experts through HLS. The developed flow is built around simple templates so that SW engineers and HW engineers alike can easily make use of HLS and providing a full flow from HLS to a state-of-the-art configurable FPGAs composed of embedded processors and FPGAs, e.g., Xilinx Zynq FPGAs. The proposed flow makes the use of democratizes using the FPGAs, and shortens the design time substantially. In order to verify that the proposed flow is effective, extensive experimental results were conducted. According to the measured results, these benchmarks could be accelerated by mapping the computationally intensive kernel on the FPGA. All of this analysis and results were made to ZedBoard Zynq - 7000 ARM / FPGA SoC Development Board using Xilinx 's tool.