Fault Tolerance in Motion Planning Applications
Presently, the technology advancement in batteries has come to a standstill. High performance computing systems requiring high power currently demand expensive cooling arrangements. Hence, while designing any portable system there must be more emphasis on devices which consume low power. While designing motion planning applications, the primary focus is on minimizing power consumption as these systems entail converting advanced level description of work into lowlevel descriptions for the operation. It also requires exploring a system configuration space of one or more convoluted structural bodies for a collision-free path that connects source to the destination while fulfilling restrictions enforced by the obstacles. For maintaining reliability of motion planning applications, systems traditionally use general redundancy, check-pointing, error checking and hardware guard bands. Though these processes consume lower power, they are more prone to hardware errors, which at times leads to catastrophic failures. Therefore, to minimize the effect of these hardware faults, we are analyzing the performance of distinct types of fault tolerant techniques by injecting faults in the motion planning algorithm.