Low-Power Techniques for Resolution and Frequency-Reconfigurable Data Conversion for Sensor-Based Applications
Srinivasan, Sharath Ranga
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Owing to the rapid technological advancements, the area of Wireless Sensor Networks has seen a Tremendous growth and are instrumental in a multitude of applications ranging from health monitoring to space exploration. Sensor networks consist of completely autonomous self-powered multiple sensor nodes that assimilate, process and transmit information, either continually or based on an event, in a distributed fashion. Although they provide innu-merable possibilities, battery size is scaled down to match the footprint of the device, and therefore, the energy-eﬃciency of the electronic circuitry is crucial in improving the lifetime of sensor nodes. An energy-eﬃcient fexible analog-to-digital converter (ADC), which is an important com-ponent of any sensor node, has been proposed. The conversion speed and resolution of the proposed ADC architecture can be easily reconﬁgured, enabling the option to ﬁne-tune the power consumption and performance based on the application at hand. A wide range of adjustable sampling rate of 500 Samples/Sec - 200 KSamples/Sec and resolution from 6-10 bits has been targeted in this work. In this dissertation, a new switching technique for successive-approximation ADC has been presented that is 90.4% more energy-eﬃcient than the conventional architecture. Detailed analysis along with simulation and chip measurement results prove the robustness of the proposed ADC.