Zhou, Dian
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Dian Zhou joined the UT Dallas faculty in 1999 as a full professor in the Department of Electrical Engineering. His research interests include:
- High Speed and Low Power VLSI Circuits
- SoCs
- Analog IC Performance Optimization
- Silicon Biosensors
- CAD Tools and Algorithms
- Biomedical Electronics
Works in Treasures @ UT Dallas are made available exclusively for educational purposes such as research or instruction. Literary rights, including copyright for published works held by the creator(s) or their heirs, or other third parties may apply. All rights are reserved unless otherwise indicated by the copyright owner(s).
Recent Submissions
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Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network
(Institute of Electrical and Electronics Engineers Inc., 2019-03-25)Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. ... -
Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis
(Institute of Electrical and Electronics Engineers Inc., 2019)In this paper, a novel multi-objective Bayesian optimization method is proposed for the sizing of analog/RF circuits. The proposed approach follows the framework of Bayesian optimization to balance the exploitation and ... -
Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis
In this paper, a novel multi-objective Bayesian optimization method is proposed for the sizing of analog/RF circuits. The proposed approach follows the framework of Bayesian optimization to balance the exploitation and ... -
An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3D ICs
Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time consuming for the drop test simulation, therefore, the fast numerical ... -
An Efficient Bayesian Yield Estimation Method for High Dimensional and High Sigma SRAM Circuits
With increasing dimension of variation space and computational intensive circuit simulation, accurate and fast yield estimation of realistic SRAM chip remains a significant and complicated challenge. In this paper, du ... -
A General Graph Based Pessimism Reduction Framework For Design Optimization Of Timing Closure
In this paper, we develop a general pessimism reduction framework for design optimization of timing closure. Although the modified graph based timing analysis (mGBA) slack model can be readily formulated into a quadratic ...
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