Schaefer, Benjamin Carrion
Benjamin Carrion Schaefer joined the UT Dallas faculty in 2016 as an Assistant Professor of Electrical Engineering. His research interests include:
- VLSI Design
- Reconfigurable Computing
- High-Level Synthesis
- High-Level Synthesis Design Space Exploration
- Hardware Security
- C-based SoC Design
- Approxinate Computing in High-Level Synthesis
- HW Diversity for Reliability
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(Elsevier Science B.V., 2018-08-23)The design of integrated circuits (ICs) is typically done using low level Hardware Description Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full controllability of the generated hardware ...
Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis (Institute of Electrical and Electronics Engineers Inc., 2019-03)Commercial High-Level Synthesis (HLS) tool vendors have started to enable ways to protect Behavioral IP (BIPs) from being unlawful used. The main approach is to provide tools to encrypt these BIPs which can be decrypted ...
(Institute of Electrical and Electronics Engineers Inc., 2019-03-25)Fault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through ...
(Institute of Electrical and Electronics Engineers Inc., 2019-03-25)Widespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit ...
Continuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often ...