Explicitly Quantum Mechanical Silicon Complementary-Metal-Oxide Semiconductor Devices
Enormous growth in silicon large scale integrated circuits (IC) has been accelerated by reducing the size of their fundamental elements such as complementary-metal-oxide-semiconductor (CMOS) transistors over the past fifty years. Quantum effects will become extremely important when the device length scale becomes smaller than the mean free path of an electron in the conduction band, which is close to scale of hundreds of silicon atoms, approaching the limit of Moore’s law. Quantum transport demonstrated as negative differential transconductance (NDTC) has been discovered in quantum well (QW) n-channel metaloxide-semiconductor (NMOS) transistors fabricated on an industrial 45 nm technology node silicon CMOS process line. NDTC regimes provide a new current-voltage transfer function that was exploited to build a folding frequency multiplier circuit using only one single QW NMOS transistor, resulting in significant circuit simplification and quiescent power reduction. Intrinsic gain measurements on silicon QW NMOS transistors show that these devices can have negative gain with magnitude up to 2.5 at room temperature, which is the prerequisite to build amplifier and oscillator applications. With the downsizing of silicon devices, a single defect inside a device such as a trap at the Si/SiO₂ interface of a CMOS transistor, plays a more and more important role in reducing device stability and limiting device sensitivity. The random telegraph signal (RTS) noise that is generated by random capture and emission of charge carriers in the inversion channel by static traps, has been observed in the source-drain current of silicon quantum mechanical NMOS transistors with current fluctuation up to 76%. Most interestingly, the switching rate of RTS gradually diminished to zero at 15 K over time scale of one to two hours, while keeping the current fluctuation stable. This decay in the switching rate may be due to a metastable oxygen vacancy defect that gradually repairs itself after repeated capture and emission of charge, deactivating the trap defect, suggesting a mechanism to eliminate at least some forms of RTS through a “cryogenic anneal”. As silicon devices are scaled down, it may become possible to build silicon thermoelectric generators (TEGs) using silicon nanowires (NW) or other forms of nanostructured silicon because of a potential large reduction in the phonon contribution to thermal conductivity, resulting in a large figure-of-merit (ZT) two orders-of-magnitude greater than bulk silicon. TEGs can recycle waste heat into electrical power, have applications ranging from on-chip thermal management embedded into ICs to environmental energy sources for low-power microsensors in the Internet-of-Thins (IoT). Very high specific power generation capacity up to 29 µW·cm⁻²K⁻², which compares favorably to that of (Bi,Sb)₂(Se,Te)₃ based TEGs, has been observed in silicon NW TEGs fabricated on an industrial 65 nm technology node silicon CMOS process line. This high specific power capacity results from the ability of CMOS processing to fabricate a very high areal density of thermocouples while keeping packing fraction low and to control parasitic electrical and thermal impedances. These silicon TEGs can be seamlessly integrated with commercial scale silicon CMOS microelectronic circuits at very low marginal cost.