Enabling CAD Support for the Field Programmable Transistor Array
This thesis concerns the development and verification of a CAD flow for a Field Programmable Transistor Array, that eases the task of creating and implementing a bit stream for the FPTA. The CAD flow takes in the behavioral Verilog file as the input and produces the bit stream. Two case studies have been explained in the thesis, also a setup which is required to load in this bit stream into the FPTA hardware has been described. This helps to implement any digital design in the FPTA hardware and test the result giving inputs directly from a PC and reading out the outputs.