Sechen, Carl M.

Permanent URI for this collectionhttps://hdl.handle.net/10735.1/7595

Carl Sechen is a Professor of Electrical Engineering. His research interests are primarilly focused on "the design and computer-aided design of integrated circuits." Ongoing projects include:

  • Energy-Efficient DSP Block Design
  • Low-Power (Sub-Threshold) Highdefinition Video Decoder Design
  • Area-Efficient and Reliable Embedded DRAM and SRAM Design
  • Cell Sizing/Selection for Global Power Minimization in Digital Integrated Circuits
  • Variational Sensitivity Reduction and Yield Enhancement
  • Cell Library Optimization
  • Time-to-Digital Conversion
  • Crystalfree High-Precision Oscillator Design
  • All-Digital Analog-to-Digital Converter Design

Browse

Recent Submissions

Now showing 1 - 1 of 1
  • Thumbnail Image
    Item
    Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming
    (Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, Yiorgos; 110195631 (Sechen, CM); Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, Yiorgos
    Widespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, concerted interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction and usage of ICs has surfaced. To this end, in this paper we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication TRAnsistor-level Programming (TRAP). We introduce a transistor-level programmable fabric and we discuss its unique advantages towards design obfuscation, as well as a customized CAD framework for seamlessly integrating this fabric in an ASIC design flow. We theoretically analyze the complexity of attacking TRAP-obfuscated designs through both brute-force and intelligent SAT-based attacks and we present a silicon implementation of a platform for experimenting with TRAP. Effectiveness of the proposed method is evaluated through selective obfuscation of various modules of a modern microprocessor design. Results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks, while incurring an order of magnitude less area, power and delay overhead. © 2019 EDAA.

Works in Treasures @ UT Dallas are made available exclusively for educational purposes such as research or instruction. Literary rights, including copyright for published works held by the creator(s) or their heirs, or other third parties may apply. All rights are reserved unless otherwise indicated by the copyright owner(s).