Background Analog and Digital Calibration Techniques for Pipelined ADC’s

dc.contributor.advisorChiu, Yun
dc.creatorSarkar, Sudipta
dc.date.accessioned2017-06-29T12:00:12Z
dc.date.available2017-06-29T12:00:12Z
dc.date.created2017-05
dc.date.issued2017-05
dc.date.submittedMay 2017
dc.date.updated2017-06-29T12:00:12Z
dc.description.abstractA digital background calibration technique to treat capacitor mismatch, residue gain error and nonlinearity in a pipelined analog-to-digital converter (ADC) based on the split-ADC architecture (J. McNeill et al., “Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE J. of Solid-State Circuits, vol. 40, pp. 2437-2445, Dec. 2005) is reported. Although multiple works have been reported before on the split-calibration of pipelined analog-to-digital converters, none of them is comprehensive, i.e., capacitor mismatch, residue gain error and nonlinearity are never treated in one work at the same time. We, for the first time, recognize the multistage pipelined ADC with residue non-linearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively. Secondly, an 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing with an area-efficient 8b offset calibration DAC. A prototype in 28nm Complementary Metal Oxide Semiconductor (CMOS) achieves 6.8 effective number of bits (ENOB) and 50fJ/c-s at DC and 6.3 ENOB and 68fJ/c-s at Nyquist, at a sample rate of 1.3GS/s. The measured SNDR/SFDR improve from 29.2/40.7dB to 42.6/57.7dB after calibration. The active area is 0.05mm2.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10735.1/5458
dc.language.isoen
dc.rightsCopyright ©2017 is held by the author. Digital access to this material is made possible by the Eugene McDermott Library. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
dc.subjectPipelined ADCs—Calibration
dc.subjectLeast squares
dc.subjectComparator circuits
dc.subjectMetal oxide semiconductors, Complementary
dc.titleBackground Analog and Digital Calibration Techniques for Pipelined ADC’s
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical Engineering
thesis.degree.grantorUniversity of Texas at Dallas
thesis.degree.levelMasters
thesis.degree.nameMSEE

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