Switched-capacitor Featured Integrated Power Circuit Design for Next-generation Power Management
The rapid proliferation of Internet of Things (IoTs), automotive and consumer electronics establishes strong demands on small system volume, low energy consumption and high level of security. As a key part of these electronic systems, this drives the power electronics to be unprecedentedly compact, efficient and reliable. Consequently, switched-capacitor (SC) power circuits, as an unique family of power electronic circuits, have seen their promising roles in improving power density, adaptability and design flexibility. However, severe design challenges such as power passive implementations, substantial on-die power loss and critical chip activities leakage must be addressed thoroughly. Accordingly, a set of SC featured integrated power circuits are presented in this dissertation to address the above challenges, which have tremendous significance for next-generation power management. Firstly, a reconfigurable three-stage SC DC-DC converter is proposed to extend input range for wireless sensor applications. A three-stage SC topology is constructed by using four fundamental 2:1 SC unit cells to realize eight step-down and step-up conversion ratios with series, parallel and series-parallel configurations while retaining low complexity. A bootstrap rail sharing technique is introduced to implement highly efficient and self-powered gate drivers for power switches. An adaptive pulse emulated hysteretic control improves load transient response and adjusts quiescent power adaptively with frequency-dependent biasing technique. Secondly, a monolithic tri-state SC DC-DC converter is designed for high power density in IoT devices. A tri-state SC topology is presented to reduce voltage stresses on power switches, enhance integrated MOS capacitance density and lower switching noise. It enhances power delivery greatly while achieving decent efficiency with on-die power loss reduction. Two-dimensional multiplechannel interleaving operation increases the equivalent switching frequency largely to further reduce switching noise and improves light-load efficiency with active channel modulation. Thirdly, a high step-down ratio hybrid SC DC-DC converter is developed in this dissertation. The proposed converter adopts the front-end SC power circuits to withstand high input voltage stress and lower switching node voltages in the following inductive topology. Thus, the on-duty time of the converter is extended, and low voltage power devices are used for efficient and fast switching. The online flying capacitor voltage (VCF) rebalancing scheme adaptively adjusts the charge and discharge times of flying capacitors to minimize power mismatch and improve device reliability in steady state. The in-situ precharge rate regulation technique precisely controls two different charge rates of flying capacitors at the start-up, avoiding power device breakdown. Lastly, this dissertation presents an SC-assisted power cipher to improve hardware security against power side-channel attacks. With a SC charge reshaper, the proposed power cipher adopts random charge shaping technique to only encrypt input power profile by using noise injection, supply masking and switching randomization. A parallel encryption interface is designed to manage the interactions between power and security strictly without shoot-through current and regulate the charge reshaper with random ON-time control for minimal power and performance overhead. In this dissertation, the first reconfigurable three-stage SC DC-DC converter is implemented and verified with fully transistor-level HSPICE simulations and the other three SC featured integrated power circuits are fabricated on silicon and measured to successfully validate proposed converter topologies and operation schemes. These experimental results provide strong evidences that the SC power circuits can be integrated as an essential part of next-generation power management strategically to achieve optimal performances among power density, efficiency and security design matrix.