Testability of Active Analog Circuits Using Sensitvity Analysis

Date

2019-05

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Abstract

Even though analog circuits occupy a small portion of silicon area on a system-on-chip, they contribute to as much test cost as digital circuits. Like digital circuits, analog circuits are also required to be tested to increase the system performance. Analog circuit testing has been done in the past with ad hoc methods, and accurate metrics for test criteria are being explored to precisely diagnose the failures in their operation. In this work, we present two methodologies to explore testability of analog circuits. Firstly, the faults induced by deviations in components are detected through multi-frequency test based on normalized sensitivity analysis. Final compaction of the test frequencies is done using a covering table optimization method. In this methodology, test frequency compaction and choice of observation points are based on a novel notation of fault equivalence and sensitivity curves. Our case study shows this method can effectively minimize the test time and sinusoidal test frequencies to separate the fault-free and faulty operations of the circuit under test for all faulty components. Second, we propose a methodology to investigate catastrophic fault testability and isolation ability in analog circuits by analyzing the fault effect on circuits gain. In our approach, catastrophic faults are modeled as opens and shorts for analog components and are introduced into transfer function. Fault detection is based on sensitivity tolerance analysis. Based on Isolation Ability of a test frequency and Sensitivity Rank, our methodology, then, will choose the test frequencies by which the faulty components are identified. For experimentation, analog filters including an active band-pass filter are studied, and the test set is validated through SPICE simulations.

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Keywords

Analog integrated circuits, Integrated circuits—Fault tolerance, Failure analysis (Engineering), Systems on a chip

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©2019 Ajaykumar Adha

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