Utilization of Post-fabrication Calibration in Thwarting Process Variation and Analog IP Piracy
The development of CMOS manufacturing technologies facilitates both the continuous scaling of device feature size and an increasing number of semiconductor companies outsourcing their ICs to third-party fab houses. This brings two unique challenges to analog/RF devices. With downscaling, process variation becomes intense and inevitably results in higher yield loss. Thus, Analog/RF design engineers turn to moderate approaches for increasing yield, but at the cost of lower performance. With manufacturing outsourcing, the protection of circuit intellectual property (IP) has become a critical factor. Among the various threats that target the IP of semiconductor devices, counterfeiting, overproduction, and unauthorized use are considered the three most significant issues that cause billions of dollars of lost revenue. Notably, the fundamental mechanism for addressing both of these two challenges can be the same: Post-fabrication calibration. Each device can be designed to be calibrated or unlocked after fabrication in order to thwart both process variation and analog IP piracy. In this work, we propose (i) Statistical post-fabrication calibration of analog/RF devices for performance optimization and reduce yield loss; (ii) Statistical self-calibration with integrated learning machine; (iii) Preventing the unauthorized use of analog/RF ICs through performance locking. We demonstrate these methods and verified these results with two chip designs fabricated in Globalfoundries 130nm RF CMOS.