Effective High-Level Synthesis Design Space Exploration Through a Novel Cost Function Formulation

Date

2020-08

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Abstract

In the last few decades, Integrated Circuits (IC) designers have had to manually translate behavioral description into Register-Transfer Level (RTL) code (e.g. Verilog or VHDL). High-Level Synthesis (HLS) automates this process. HLS has many advantages as compared to specifying hardware at the RT-Level. One big advantages is that the behavioral description only needs to be designed and verified once, but allows to generate RTLs with different characteristics by simply specifying different synthesis options. This opens the door to perform a fully automatic Design Space Exploration (DSE). The main goal in HLS DSE is to find Pareto-optimal micro-architectures for the given untimed behavioral description. For large untimed descriptions an exhaustive enumeration of all possible synthesis options combinations is not possible, hence heuristics are required. This work presents three metaheuristic algorithms to address this issue: Simulated Annealing (SA), Genetic Algorithm (GA) and Ant Colony Optimization (ACO). These algorithms are originally used to solve Single-Objective (SO) problems whereas DSE is Multi-Objective (MO), i.e. area vs. performance. To convert the MO problem into a SO, this work proposes a new method called ξ-constraint to do the conversion, and compares the result with the traditional method (weighted sum as cost function) for all three algorithms.

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Integrated circuits, Electronic data processing, System design -- Data processing, Metaheuristics

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©2020 Yiheng Gao. All rights reserved.

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