A Machine Learning Based Hard Fault Recuperation Model for Approximate Hardware Accelerators

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dc.contributor.authorTaher, Farah Naz
dc.contributor.authorCallenes-Sloan, J.
dc.contributor.authorSchaefer, Benjamin Carrion
dc.contributor.utdAuthorTaher, Farah Naz
dc.contributor.utdAuthorSchaefer, Benjamin Carrion
dc.date.accessioned2019-07-12T16:15:44Z
dc.date.available2019-07-12T16:15:44Z
dc.date.created2018-06-24
dc.descriptionFull text access from Treasures at UT Dallas is restricted to current UTD affiliates (use the provided Link to Article). Non UTD affiliates will find the web address for this item by clicking the "Show full item record" link, copying the "dc.relation.uri" metadata and pasting it into a browser.
dc.description.abstractContinuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often tolerant to inaccuracies in their outputs, e.g. image and digital signal processing applications. At the same time, permanent faults are escalating due to process scaling and power restrictions, leading to erroneous outputs. To address this issue, in this paper, we propose a low-cost, universal fault recovery/repair method that utilizes supervised machine learning techniques to ameliorate the effect of permanent fault(s) in hardware accelerators that can tolerate inexact outputs. The proposed compensation model does not require any information about the accelerator and is highly scalable with low area overhead. Experimental results show, the proposed method improves the accuracy by 50% and decreases the overall mean error rate by 90% with an area overhead of 5% compared to execution without fault compensation.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.identifier.bibliographicCitationTaher, F. N., J. Callenes-Sloan, and B. C. Schafer. 2018. "A machine learning based hard fault recuperation model for approximate hardware accelerators." Proceedings - Design Automation Conference 55, 137710: art. 80, doi:10.1145/3195970.3195974
dc.identifier.isbn9781450357005
dc.identifier.urihttps://hdl.handle.net/10735.1/6683
dc.identifier.volume137710
dc.language.isoen
dc.publisherThe Association for Computing Machinery
dc.relation.isPartOfProceedings - Design Automation Conference, 55
dc.relation.urihttp://dx.doi.org/10.1145/3195970.3195974
dc.rights©2018 ACM
dc.subjectFault-tolerant computing
dc.subjectMachine learning
dc.subjectSupervised learning (Machine learning)
dc.subjectArtificial intelligence
dc.subjectComputer-aided design
dc.subjectSignal processing--Digital techniques
dc.subjectEnergy consumption
dc.subjectComputers
dc.subjectSelf-organizing systems
dc.subjectSystems on a chip
dc.subjectParallel programming (Computer science)
dc.titleA Machine Learning Based Hard Fault Recuperation Model for Approximate Hardware Accelerators
dc.title.alternativeProceedings - Design Automation Conference; 55th Annual Design Automation Conference, Dac 2018
dc.type.genrearticle

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Schaefer, Benjamin Carrion