Field Programmable Gate Arrays (FPGAs) are used not only for rapid prototyping but also for implementing very high-performance computing engines. Advancements in big data, machine learning, and neural network are increasing FPGA devices in popularity. The statistics show that most of the Integrated Circuits and FPGAs are damaged due to overheating or high thermal gradient. Many companies declare breaks to Moore’s law due to very high power densities in ICs. GPUs have an ability to work at few thousands GFLOPS processing power. Single GPU device consumes hundreds of watts of power. FPGAs are cheap and power efficient. However, power consumption and dissipation trend in FPGAs in increasing for many applications.

This thesis focuses on thermal aware placement for FPGA mapped designs. In order to accurately model the effect of physical locations of a logic block on the overall thermal profile, we need to have accurate power and temperature estimation methods. We present the results of a modified placement algorithm, that takes accurate logic block level power estimates into account. We have presented a modified design flow that is built on top of the Versatile Placement and Routing framework from University of Toronto. Our results implicate a well improved thermal profile for FPGA mapped designs.