Far Infrared Detection and Photonic Components in Complimentary Metal-oxide Silicon (CMOS) Technologies

Consumer applications of Infrared (IR) and Far Infrared (FIR) imaging are emerging. These systems require fabrication of detectors on a membrane, heterogeneous integration with read-out IC, and specialized packaging, which all increase cost. To lower the cost of Far Infrared imaging circuits, this dissertation investigated feasibility of realizing the circuits using CMOS. Implementing an electronic circuit becomes increasingly challenging in the Far infrared region of the spectrum since the state-of the-art active solid-state devices no longer have gain. First, this work proposed a metal-n+ silicon junction that is fabricated in a 130-nm CMOS process without process modifications. Its cut-off frequency (fT) is expected to be greater than 5 THz and flicker noise corner frequency is less than 10 kHz at a bias current of 100 nA. This is the highest fT for any junctions fabricated in silicon technologies to date. The parasitic effects of metal interconnect on the fT of junctions and diodes are explored and techniques to overcome the challenges are demonstrated by increasing the fT of Poly-Gate-Separated Schottky Barrier Diodes (PGS SBD) from ~2 THz to 2.7 THz. Second, challenges for characterization of on-wafer devices with an fT of over 1 THz are investigated and a de-embedding method (Sub-array-SHORT) for improving the measurement reliability is proposed. The proposed technique overcomes the limitations of vector network analyses of structures with a large ratio of imaginary and real parts (|X|/R) of their impedance. Measurements and comparisons are performed to verify the effectiveness of the proposed method. The %-variations of measured fT and series resistance over the measurement frequency range (50 to 55 GHz) and over the samples are reduced by ~50% compared to the measurements using a conventional OPEN structure. Proper scaling of the estimated resistance and capacitance with the number of device cells indicates that the proposed de-embedding technique provides estimations of resistance, capacitance, and fT with improved accuracy. For the first time, 20-THz electronic detection using foundry CMOS technologies is demonstrated. The effects of thermal and electronic detections are separated noting that the output from thermal and electronic detections can have opposite signs. A 20-THz PGS SBD detector using a 110-nm CMOS process without process modifications is integrated with an on-chip Lock-In Amplifier. Detectors with larger aperture sizes for FIR detection are implemented. It occupies an area of 82 µm2 . The peak optical responsivity of 29.8 V/W and shot noise limited NEP of 2.2 nW/√Hz are achieved. Additionally, a 20-THz detector using the proposed unsilicided metal-n + junction is fabricated using a standard 130-nm CMOS technology once again without any process modifications. The pixel area is 8.6 µm2 . This is significantly smaller than other detectors reported in the literature which makes it a good potential candidate for large detector arrays. The measurements show that its output is higher at low bias conditions at which noise is smaller compared to the PGS SBD detectors. The performance is better than other previously reported state-of-the-art and commercially available FIR detectors. Finally, the frequency responses of the antennas are verified by measurements using an FTIR. To characterize the detectors, a computer controlled low-cost wideband imaging setup is constructed. A blackbody light source is utilized along with a wideband pyroelectric thermal detector that is combined with an automatic 3-axis stage.