An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3D ICs

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dc.contributor.authorZhou, H.
dc.contributor.authorZhu, H.
dc.contributor.authorCui, T.
dc.contributor.authorPan, D. Z.
dc.contributor.authorZhou, D.
dc.contributor.authorZeng, X.
dc.date.accessioned2019-07-26T17:15:04Z
dc.date.available2019-07-26T17:15:04Z
dc.date.created2018-07-05
dc.descriptionFull text access from Treasures at UT Dallas is restricted to current UTD affiliates (use the provided Link to Article). Non UTD affiliates will find the web address for this item by clicking the "Show full item record" link, copying the "dc.relation.uri" metadata and pasting it into a browser.
dc.description.abstractDrop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time consuming for the drop test simulation, therefore, the fast numerical approach is generally needed to reduce the computational cost. In this paper, we propose an efficient drop-test simulator for through-siliconvia (TSV) based three-dimensional integrated circuit (3D IC) to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. And second, an equivalent structureembedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop-test simulator can achieve 7.03× speedup in comparison with the conventional FEM-based solver. It is demonstrated in the paper in the paper through several examples with multi chip layers, of which each chip layer consists of an 8 × 8 TSV array, that the proposed simulator can be widely applied to reliability analysis of 3D ICs under drop impact.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.description.sponsorshipNational Key Research and Development Program of China grant 2016YFB0201304, National Natural Science Foundation of China Research Project grants 61376040, 61574046, 61774045, 61574044, 61628402, 11771440, 91530323, and 11101417. Key Research Program of the Chinese Academy of Sciences grant XDPB11,
dc.identifier.bibliographicCitationZhou, H., H. Zhu, T. Cui, D. Z. Pan, et al. 2018. "An improved domain decomposition method for drop impact reliability analysis of 3d ICs." IEEE Transactions on Components, Packaging and Manufacturing Technology 8(10): 1788-1799, doi:10.1109/TCPMT.2018.2853157
dc.identifier.issn2156-3950
dc.identifier.issue10
dc.identifier.urihttps://hdl.handle.net/10735.1/6736
dc.identifier.volume8
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.urihttp://dx.doi.org/10.1109/TCPMT.2018.2853157
dc.rights©2018 IEEE
dc.source.journalIEEE Transactions on Components, Packaging and Manufacturing Technology
dc.subjectReliability
dc.subjectChip scale packaging
dc.subjectIntegrated circuits—Design and construction
dc.subjectIntegrated circuits
dc.subjectIterative methods (Mathematics)
dc.subjectNumber theory
dc.subjectAccelerated life testing
dc.subjectSimulation methods
dc.subjectTiming circuits
dc.subjectThree-dimensional integrated circuits
dc.titleAn Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3D ICs
dc.type.genrearticle

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