Design of a High-Performance DC Power Cycling Test Setup for SiC MOSFETs

dc.contributor.ORCID0000-0001-6912-7219 (Akin, B)
dc.contributor.authorYang, Fei
dc.contributor.authorUgur, Enes
dc.contributor.authorPu, Shi
dc.contributor.authorAkin, Bilal
dc.contributor.utdAuthorYang, Fei
dc.contributor.utdAuthorUgur, Enes
dc.contributor.utdAuthorPu, Shi
dc.contributor.utdAuthorAkin, Bilal
dc.date.accessioned2020-04-02T22:42:18Z
dc.date.available2020-04-02T22:42:18Z
dc.date.issued2019-03-17
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractIn this paper, a high-performance DC power cycling setup dedicated for SiC power MOSFETs is presented. Different from the previous DC power cycling setup designs focusing on circuit topology and operation principle, this paper discusses the detailed design considerations to ensure the measurement accuracy and control the voltage spikes within the safe voltage range of the data acquisition (DAQ) equipment. Specifically, the transient behavior of the circuit is analyzed, and a simulation model is built in LTspice to facilitate the design. From the simulation result, it is observed that the gate timing control is critical to limit the measurement spikes. In addition, adding decoupling capacitors helps to attenuate the ringing noise in the voltage measurement. A prototype is built, and the experimental results indicate that a precise measurement can be realized with the proposed DC power cycling setup under various conditions. © 2019 IEEE.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.description.sponsorshipNational Science Foundation under the Award Number 1454311; Texas Analog Center of Excellence (TxACE) under the Task ID 2712.026
dc.identifier.bibliographicCitationYang, F., E. Ugur, S. Pu, and B. Akin. 2019. "Design of a high-performance DC power cycling test setup for SiC MOSFETs." IEEE Applied Power Electronics Conference and Exposition: 1390-1396, doi: 10.1109/APEC.2019.8721974
dc.identifier.isbn9781538683309
dc.identifier.urihttp://dx.doi.org/10.1109/APEC.2019.8721974
dc.identifier.urihttps://hdl.handle.net/10735.1/7791
dc.identifier.volume2019
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.rights©2019 IEEE
dc.source.journalIEEE Applied Power Electronics Conference and Exposition
dc.subjectAcquisition of data sets
dc.subjectSilicon carbide
dc.subjectSilicon compounds
dc.subjectElectric power transmission--Direct current
dc.subjectCapacitors
dc.subjectMetal oxide semiconductor field-effect transistors
dc.titleDesign of a High-Performance DC Power Cycling Test Setup for SiC MOSFETs
dc.type.genrearticle

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