Millimeter-wave Wideband MSK Receiver and Transmitter in CMOS
The sub-terahertz portion of the electromagnetic spectrum can provide a large bandwidth for both wireless communication and wireline communication using dielectric waveguides. To fully exploit the bandwidth, the communication systems inevitably require frequency division multiplexing. Since integrating a highly frequency-selective multiplexer and a de-multiplexer is challenging at these frequencies, use of MSK (Minimum Shift Keying) modulation with reduced out-of-band emission is a potential approach to alleviate this technical challenge. Furthermore, MSK is a constant envelope modulation and allows more power efficient operation of transmitters. This is particularly important at sub-terahertz frequencies, where the power efficiency of circuits is low. Lastly, MSK signals can be demodulated using a phase locked loop (PLL) based receiver that tracks the carrier frequency of signals incident to a receiver, which greatly relaxes the frequency synchronization requirements in both transmitter and receiver. PLL-based receivers are also simple to implement. Although MSK signals have such merits for sub-THz communication, the previously reported carrier frequency of Gilbert-mixer-based MSK transmitters is lower than 60 GHz and data rate lower than 2 Gbps. The maximum data rate of PLL-based receivers is 10’s of Mbps. Increasing the data rate of PLL-based receiver and generation of high-data rate MSK signals are the main topics of this dissertation. First, a 180-GHz MSK receiver using a phase-locked loop (PLL), which self-synchronizes carrier frequency is demonstrated. The mixer first receiver is fabricated in a 65-nm CMOS process. A double balanced anti-parallel-diode-pair sub-harmonic mixer performs the phase detection, reducing the frequency of LO by half. Tunable zeros realized by series inductors are used to improve the stability and to increase the data rate handling capability. Without external LO synchronization, the receiver demodulates MSK signals at 10 Gbps with a bit error rate (BER) of < 10-12 and at the maximum data rate of 12.5 Gbps with a BER of 3.8×10-5 . The BER at 10 Gbps is the lowest and the data rate of 12.5 Gbps is the highest for PLL receivers. Second, high data rate 180-GHz MSK modulated signals for dielectric waveguide communication are generated using a transmitter fabricated in 65-nm CMOS. To accomplish this, techniques for controlling the relative phases of half-sine shaping signal and data, “Misaligned-to-Aligned” are proposed and demonstrated. Limited by the instrumentation for MSK signal analyses, the eyes of transmitted MSK signals have been verified for a data rate up to 10 Gbps. The MSK signal generator provides a 5X higher data rate among all the previously reported MSK transmitters at a 3X higher carrier frequency. Thirdly, a dual-band minimum shift keying (MSK) transmitter operating at 180 GHz and 315 GHz is demonstrated in 65-nm CMOS. The transmitter incorporates the data encoder and wideband I/Q phase alignment for MSK signal generation. Limited by the instrumentation for the MSK signal analyses, the 315-GHz channel is used to form a 10-Gbps link at BER= 5×10-5 with an on-chip PLL-based receiver. It has increased the highest carrier frequency of MSK signal generation from 180 GHz to 315 GHz. This work also demonstrates the first single-chip transmitter in CMOS that supports frequency division multiple access (FDMA) communication above 150 GHz.