CAD Tools for PCB Reverse Engineering and IC Interconnect




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This thesis will introduce two different CAD tools, MTBOM, and SMOR, for two specific applications. We developed our original tool, MTBOM, Metal Trace to Bill Of Materials automation for Printed Circuit Board Reverse Engineering (PCB-RE). Here, we assumed that the PCBs are devoid of any components or silkscreens, with only the wiring traces accessible on the various layers. This models the scenario where the PCBs are damaged and/or discarded. PCB-RE is highly useful for design verification and fault isolation of essential legacy systems, where it often happens that some parts in a legacy system are required to be replaced while there are no records in system documentation; MTBOM can offer a solution to such a situation identifying such parts by simply metal analysis. We demonstrate that our PCB-RE tool extracts the correct Bill of Materials (BoM) for ten different PCBs by analyzing primarily the metal layers. The proposed PCB-RE tool MTBOM detected every integrated circuit (IC) on the PCBs with no false positives or negatives. This scheme also identifies passive components, such as resistors, capacitors, and inductors. In SMOR, we have proposed a Simple Model Order Reduction approach for parasitic extrac- tions of metal interconnects. Parasitic EXtractions (PEX) of the metal interconnects are complex, consisting of millions or more passive elements. Consequently, the space requirements for PEX are enormous, and the simulation times are unacceptably long. The model order reduction method called PACT in Synopsys’ HSPICE simulator significantly reduces the simulation times. However, in SMOR, we have developed a simple technique to minimize each non-branching metal segment extraction to a single RC pi-element. And then, we can reduce the aggregate RC branches based on fundamental network analysis theorems. The effective delay to any number of projected nodes is modeled with the minimum number of RC components. When we applied SMOR on the C880 (an 8-bit ALU) ISCAS benchmark circuit for GF 12nm FinFET technology, it resulted in over a 10X reduction in R, and about 3X reduction in C size, while maintaining 100% delay accuracy and featuring approximately 3X speed up while applying on HSPICE and can make 73% speed up in simulation time while integrated with PACT compared to using PACT only. This dissertation presents MTBOM in its first three chapters, and we dedicate the last chapter to delivering SMOR.



Engineering, Electronics and Electrical