FPGA Based KNN Search Engine




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Today's processing applications, such as machine learning and text mining, are becoming more complex and process large amounts of data. Computational demands imposed by such applications are not easily met by traditional computing platforms. There is increasing shift towards GPGPUs (General Purpose Graphics Processing Units) and FPGAs (Field Programmable Gate Arrays) for executing high performance applications. Both of these devices can be used to process more efficiently large datasets by working in parallel. The complex applications are made of many smaller algorithms such as K Nearest Neighbor (KNN), that enable themselves to be performed in parallel and are easy to speed up. Finding an architecture that can utilize this more efficient technology to accelerate the algorithms would improve the run time of the original application. Intel’s next generation of Xeon server grade processors will include FPGAs and allow for faster large data parallelization. The ZedBoard, having the Xilinx Zynq XC7Z020 architecture that provides approximately 85,000 logic cells for the accelerator as well as the ARM Cortex-A9 for control, can be thought of as a small scale version of the Xeon server. Accelerators implemented on the ZedBoard utilize the AXI interfaces that allow for compatibility and interchangeability between many other accelerators. This thesis discusses in detail how to design and implement the KNN algorithm on the Xilinx Zynq architecture in order to improve its run time. Also discussed are performance comparisons between the hardware-accelerated implementation and its software implementation.



Field programmable gate arrays, Nearest neighbor analysis (Statistics), Computer architecture



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