Routing Methods for Transistor-level Programmable Fabrics

You may be surprised if someone tells you that chips are the new oil. Economic historian Chris Miller, in his new book Chip War, states that chips are the world’s most critical resource, and explains how the semiconductor came to play a critical role in modern life. Today, military, economic, and geopolitical power are built on a foundation of chips. In many ways, our world is “built” on semiconductors. As the impact of digital on lives and businesses has accelerated, semiconductor markets have boomed, with sales growing by more than 20 percent to about $600 billion in 2021. McKinsey [1] analysis based on a range of macroeconomic assumptions suggests the industry’s aggregate annual growth could average from 6 to 8 percent a year up to 2030. The result? A $1 trillion dollar industry by the end of the decade, assuming average price increases of about 2 percent a year and a return to balanced supply and demand after current volatility. The semiconductor industry has evolved over the past few decades in all fields, specifically chip design, manufacture, packaging and testing. The chip design methodology has also advanced with the continuous scaling of the feature size in Very Large Scale Integrated circuits (VLSI). The tiny chips are one of the most difficult devices to design in the world, following a fairly long chip design flow, all design flow steps are necessary and equally important; if mistakes are introduced in any step, this may make the whole chip unable to work as expected. Among those numerous steps, routing is to connect all components in the circuit together properly and efficiently. Programmable logic devices, such as Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLDs), have grown in popularity in a myriad of applications since their inception due to their reconfigurability and lower non-recurrent engineering costs when compared to Application Specific Integrated Circuits (ASICs). To keep pace with growing application needs and process technology improvements, FPGAs have traditionally chosen full custom chip design approaches. However, embedded FPGAs (eFPGAs) have been introduced to enable ASICs to be less application specific, thereby producing the need for an agile design approach to accelerate the eFPGA design process. A TRAnsistor-level Programmable fabric (TRAP) has received interest recently as a more compact eFPGA for hardware obfuscation, in which a selected sensitive portion of the design is implemented in the eFPGA, and the residue is implemented as ASIC. Unfortunately, state-of-the-art routing tools are not fully compatible with the new architecture. In this work, we develop routing methods customized for the TRAP fabric, to address all the unique architecture requirements. Experimental results corroborate that the proposed routing methods for the transistor-level programmable fabric are working as needed and are fully automated with a single push-button solution.