Approximate Computing Through Bitwidth Optimization

In this thesis, we propose an approximate computing methodology based on bit width optimization that reduces the internal signal’s bit widths in behavioral descriptions for HLS, and in particular SystemC in order to trade-off area and delay vs. output error. This methodology is coupled with a novel Binary search strategy for selecting the bit widths of the aforementioned internal signals in order to obtain a trade-off of Pareto-optimal configurations. In order to prove the efficacy of the proposed methodology we have implemented this methodology and tested it on six benchmarks from S2CBench v.2.2. The proposed method is abbreviated as ACdesigns, which are the approximate computing designs with error less than Emax% (tolerable maximum error). These are the designs which are obtained after the bit width reduction. Since these designs use smaller bit widths than the original, they result in less area and delay. Also, the error, area and running time are all critical parameters to get ACdesigns. Thus, we study and prove experimentally that the strategy for bit width selection takes less running time than the brute force and will eventually lead to the optimal area vs. error Pareto-optimal designs. Finally, we prove that the implementation with the proposed method is on average 20.59% more area efficient compared to static methods used in commercial HLS Tools and results in better running time over brute force method.