Metastability-zone Based Quantization for High-speed Analog-to-digital Converters
| dc.contributor.advisor | Liu, Jin | |
| dc.contributor.advisor | Bereg, Sergey | |
| dc.contributor.committeeMember | Lee, Hoi | |
| dc.contributor.committeeMember | Zhou, Dian | |
| dc.contributor.committeeMember | Carrion Schaefer, Benjamin | |
| dc.creator | Ren, Jiajun 1990- | |
| dc.date.accessioned | 2024-03-06T19:55:29Z | |
| dc.date.available | 2024-03-06T19:55:29Z | |
| dc.date.created | 2023-12 | |
| dc.date.issued | December 2023 | |
| dc.date.submitted | December 2023 | |
| dc.date.updated | 2024-03-06T19:55:29Z | |
| dc.description.abstract | High-speed analog-to-digital converters (ADCs) are highly demanded in both wireless and wireline communication systems. These systems normally require 6 to 8 bits resolution for further data processing and preferrable even higher resolution in some areas like satellite communication. However, due to the weak signal arrived at receivers, the system effective least significant bit (LSB) becomes small. In ADCs with traditional quantization technique, the LSB is always limited by the comparator offset. Meanwhile, high clock rate comparator with small LSB can easily fall into metastable state during quantization, which is a dominant source of bit-error-rate (BER). In this dissertation, a high-speed ADC quantization method based on the metastability-zones is presented. Compared with traditional comparator based quantization method, which requires sufficient regeneration time and large enough LSB to generate valid logic outputs, the proposed method can significantly reduce the regeneration time to achieve a higher sampling rate and a finer quantization scale. To prove the proposed quantization method, a MATLAB model is created for mathematically verification. Two 2-GS/s, 6-bit flash ADCs with different calibration schemes are designed in 130nm CMOS for block level verification. At the end, a 3.2-GS/s 6-bit flash ADC prototype is designed and fabricated in 65nm CMOS. The measured results show that the system achieves 5mV least significant bit, which is much smaller than the traditional flash ADCs using comparator based quantization and is in the range of comparator with interpolation technique design. At the same time, the sampling rate with proposed quantization method is higher. The figure-of-merit of 263 fJ/conv-step is the best compared with the state of the art design with similar resolution and sampling rate. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | ||
| dc.identifier.uri | https://hdl.handle.net/10735.1/10002 | |
| dc.language.iso | English | |
| dc.subject | Engineering, Electronics and Electrical | |
| dc.title | Metastability-zone Based Quantization for High-speed Analog-to-digital Converters | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.college | School of Engineering and Computer Science | |
| thesis.degree.department | Electrical Engineering | |
| thesis.degree.grantor | The University of Texas at Dallas | |
| thesis.degree.name | PHD |
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