Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

dc.contributor.VIAF110195631 (Sechen, CM)
dc.contributor.authorShihab, Mustafa M.
dc.contributor.authorTian, Jingxiang
dc.contributor.authorReddy, Gaurav Rajavendra
dc.contributor.authorHu, Bo
dc.contributor.authorSwartz, William
dc.contributor.authorSchaefer, Benjamin Carrion
dc.contributor.authorSechen, Carl
dc.contributor.authorMakris, Yiorgos
dc.contributor.utdAuthorShihab, Mustafa M.
dc.contributor.utdAuthorTian, Jingxiang
dc.contributor.utdAuthorReddy, Gaurav Rajavendra
dc.contributor.utdAuthorHu, Bo
dc.contributor.utdAuthorSwartz, William
dc.contributor.utdAuthorSchaefer, Benjamin Carrion
dc.contributor.utdAuthorSechen, Carl
dc.contributor.utdAuthorMakris, Yiorgos
dc.date.accessioned2020-03-27T16:13:01Z
dc.date.available2020-03-27T16:13:01Z
dc.date.issued2019-03-25
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractWidespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, concerted interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction and usage of ICs has surfaced. To this end, in this paper we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication TRAnsistor-level Programming (TRAP). We introduce a transistor-level programmable fabric and we discuss its unique advantages towards design obfuscation, as well as a customized CAD framework for seamlessly integrating this fabric in an ASIC design flow. We theoretically analyze the complexity of attacking TRAP-obfuscated designs through both brute-force and intelligent SAT-based attacks and we present a silicon implementation of a platform for experimenting with TRAP. Effectiveness of the proposed method is evaluated through selective obfuscation of various modules of a modern microprocessor design. Results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks, while incurring an order of magnitude less area, power and delay overhead. © 2019 EDAA.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.identifier.bibliographicCitationShihab, M. M., J. Tian, G. R. Reddy, B. Hu, et al. 2019. "Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming." Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition: 528-533, doi: 10.23919/DATE.2019.8714856
dc.identifier.isbn9783981926323
dc.identifier.urihttp://dx.doi.org/10.23919/DATE.2019.8714856
dc.identifier.urihttps://hdl.handle.net/10735.1/7597
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.isPartOfProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition
dc.rights©2019 IEEE
dc.subjectApplication-specific integrated circuits
dc.subjectComputer aided design
dc.subjectIntegrated circuit design
dc.subjectField programmable gate arrays
dc.subjectMicroprocessors
dc.subjectReverse engineering
dc.titleDesign Obfuscation through Selective Post-Fabrication Transistor-Level Programming
dc.type.genrearticle

Files

Original bundle

Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
JECS-7595-261093.07-LINK.pdf
Size:
166.44 KB
Format:
Adobe Portable Document Format
Description:
Link to Article