Enabling the Generation of Behavioral System-on Chip (SoC)




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The thesis aims to enable the generation of complete behavioral heterogenous System-on-Chip (SoC) through two main ideas: First, an automatic bus generator that takes as input the bus characteristics and memory map of all the components in the SoC generating a synthesizable behavioral description of the bus. The second, a library of synthesizable APIs to abstract away the interconnect from the different components in the SoC. This enables some unique capabilities compared to using low-level hardware description languages, i.e. Verilog or VHDL. (1) It allows to generate the entire SoC quickly. (2) It enables the generation of quick cycle-accurate simulation models that allow simulation of complete SoCs cycle-accurately. Experimental results of different types of SoC configurations show that these simulation models are substantially faster than systems described at the RT-level. (3) It allows to fully abstract away the bus interface from the different components making it very easy to change between different bus protocols. Finally, (4) it allows to change the bus architecture including arbiter and bus bit-width with minor modifications to the behavioral descriptions of the individual components. Experimental results highlight the benefits of this approach when generating complete SoCs and compares with traditional RT-Level approaches.



Systems on a chip, Logic design, Synchronous circuits