Standard Cell Library Composition Optimization for Advanced Process Nodes

The quality of standard cell libraries, which serve as the building blocks for Application Specific Integrated Circuits (ASICs), is heavily influenced by their range of logic cell functions and drive strengths. However, the sheer vastness of contemporary libraries imposes high costs and considerable challenges in generation, maintenance, and characterization, especially during technology node transitions. In response to these issues, we present a methodology that seeks the minimum subset of logic functions and drive strengths in any given ASIC standard cell library that does not sacrifice power, performance or area (PPA) compared to the use of the full library. Our methodology, which is developed around state-of-the-art Electronic Design Automation (EDA) tools, has been applied to standard cell libraries for four FinFET-based technologies (i.e., 16nm, 12nm, 7nm, and 5nm) and evaluated on a range of benchmark circuits and industrial designs. Results show that the standard cell libraries can be reduced to around 16 different combinational logic functions, a single drive for each flip-flop type, and a fraction of the full set of drive strengths and yet not sacrifice any meaningful power, performance, and area. In turn, this implies that library generation, maintenance and characterization time could be reduced by more than an order of magnitude.