Design Space Exploration for Secure and Power-efficient Microprocessor Designs

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2019-11-21

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Abstract

With increasing reliance on third-party, potentially untrusted fabrication facilities designers face increasing threat of intellectual property (IP) piracy in the form of reverse-engineering, over-production, hardware Trojans insertion etc. In this work, we propose performance locking, a variant of logic locking technique, to thwart aforementioned attacks. In the proposed provably-secure performance locking scheme, we carefully integrate additional logic into the design and protect the modified design using a secure key. Performance locking takes advantage of the design’s control and data path, and inserts additional bubbles in the pipeline when an unauthorized user tries to access the system. The locking scheme has been implemented in multiple microprocessor pipelines and effectiveness of the locking is demonstrated through register transfer level (RTL) simulation and field programmable gate array (FPGA) implementation. Our simulation results show a ∼97% performance degradation in the locked design as compared to its original version. We also evaluate trade-offs between performance, runtime, and power/area overhead for the proposed scheme. While exploring performance locking’s impact on power consumption we observed that, the state-of-the-art power estimation method is not sufficiently accurate. Specifically, the inaccuracies stem from the simplistic modeling of the design at the early stage. To this end, we present a novel a Cross-layer frAmework for accurate Power Estimation (CAPE). CAPE implements an intelligent integration of system-level and RT-level performance parameters for estimating power consumption. We propose two different approaches for the CAPE framework. Using real-life workloads, the simulation results show a 9% accuracy improvement over the state-of-the-art method of power estimation at early design stage.

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Intellectual property, Computer security, Energy consumption

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