Efficient High-level Synthesis Design Space Exploration





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To address the increase in Very Large-Scale Integration (VLSI) design complexity, companies have started to embrace High-Level Synthesis (HLS) as an alternative to traditional Register Transfer Level (RTL) VLSI design based on low-level hardware description languages (HDLs) such as Verilog or VHDL. HLS takes high level languages, such as ANSI-C, C++ or SystemC, as input and generate efficient RTL code. One of the most salient advantages of HLS is that it allows users to generate different designs by simply changing the synthesis options. Setting different combinations of these options lead to micro-architectures with different area, latency, power trade-offs. Among all the possible micro-architectures, the designer is typically only concerned about the Pareto-optimal ones. However, due to the exponential growth of the synthesis options search space, exhaustive enumerations are not possible. Thus, most work in the HLS Design Space Exploration (DSE) domain deals with the design of efficient heuristics. The main research contribution in this dissertation has been to investigate efficient HLS DSE methods. Firstly we analyse the relationship between meta-heuristics’ hyper parameters and their performance. Secondly, we introduce a new method based on transfer learning. This implies that the results from previous HLS DSE results are leveraged to more efficiently explore the search space of a new, unseen behavioral description. On the other hand, raising the level of abstraction opens the door to a new service model based on Behavioral IPs (BIPs). Unfortunately not many particular methods exist to protect the BIP providers from their BIPs being illegally distribute. In this dissertation I investigate a new business model that allows to lock the search space of BIPs by partially encrypting it. This has the benefit of allowing a new price discrimination policy. BIP consumers that want a fully visible BIP would need to pay more, while BIPs what only want a partially explorable BIP are expected to pay less. Finally, this dissertation investigates the use of embedded Field Programmable Gate Arrays (eFPGAs) in the context of BIP logic locking by judiciously extracting a portion of a BIP for HLS onto an eFPGA while mapping the rest on an Application Specific Integrated Circuit (ASIC).



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