VeriIntel2C: Abstracting RTL to C to Maximize High-Level Synthesis Design Space Exploration

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dc.contributor.authorMahapatra, Anushree
dc.contributor.authorSchaefer, Benjamin Carrion
dc.contributor.utdAuthorSchaefer, Benjamin Carrion
dc.date.accessioned2020-06-03T14:30:15Z
dc.date.available2020-06-03T14:30:15Z
dc.date.issued2018-08-23
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractThe design of integrated circuits (ICs) is typically done using low level Hardware Description Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full controllability of the generated hardware design as they allow to specify the detailed behaviour and structure of the architecture, at every single clock cycle. The main drawback of using these low level HDLs is that takes very long time to create and verify large ICs with them. Moreover, it is hard to re-use HDL code for future projects that require changes in the micro-architecture. Thus, the industry is moving the level of abstraction to C-based VLSI design where designers only have to specify the functionality of the program and High-Level Synthesis (HLS) tools generate the HDL automatically. One additional benefit of C-based VLSI design is that it enables to explore the search space of possible micro-architectures from a single behavioral description. The result of a Design Space Exploration (DSE) is a trade-off curve of Pareto-optimal designs with unique area vs. performance metrics. Most VLSI design companies have large amounts of legacy HDL code. Thus, it makes sense to have an automatic flow to convert HDL designs into behavioral descriptions (e.g. C, C++ or SystemC) optimized for HLS DSE. This implies that the generation of explorable constructs, e.g. loops and arrays, which upon exploration, lead to very different micro-architectures (e.g. loops can be unrolled or folded, arrays can be mapped to RAMs or registers). In this paper, we propose a robust RTL to C translation method called Verilntel2C to abstract RTL descriptions (written in Verilog) into ANSI-C descriptions optimized for HLS DSE by generating a large number of loops and arrays. Our method is able to generate these explorable constructs with the use of extended Hardware Petri Nets to extract the behaviour of the Verilog designs and to generate a Control Data Flow Graph (CDFG) that allows the easy identification of these constructs. From the experimental results, we are able to demonstrate that Verilntel2C expands the design space considerably and also improves the quality of design space by 55% on average compared to previous work, on a wide range of designs.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.identifier.bibliographicCitationMahapatra, Anushree, and Benjamin Carrion Schafer. 2019. "Verilntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration." Integration, the VLSI Journal 64: 1-12, doi: 10.1016/j.vlsi.2018.03.011
dc.identifier.issn0167-9260
dc.identifier.urihttp://dx.doi.org/10.1016/j.vlsi.2018.03.011
dc.identifier.urihttps://hdl.handle.net/10735.1/8665
dc.identifier.volume64
dc.language.isoen
dc.publisherElsevier Science B.V.
dc.rights©2018 The Authors
dc.source.journalIntegration, the VLSI Journal
dc.subjectComputer hardware description languages
dc.subjectPetri nets
dc.subjectIntegrated circuits—Very large scale integration
dc.subjectVHDL (Computer hardware description language)
dc.titleVeriIntel2C: Abstracting RTL to C to Maximize High-Level Synthesis Design Space Exploration
dc.type.genrearticle

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