Defect Tolerant Design: Improving Manufacturing Yield of Integrated Circuits

This dissertation presents a study on improving the manufacturing yield of integrated circuits by advocating a defect-aware circuit design approach. In the latest technology nodes, there is a growing concern regarding yield loss due to timing failures and delay degradation resulting from manufacturing complexities. Largely, these manufacturing imperfections are fixed using empirical methods such as Design for Manufacturability Guidelines (DFMGs) for the layout and process fixes that are expensive and included during the final stages of the physical design process. We propose a defect-tolerance framework for improving design yield by taking advantage of existing Electronic Design Automation (EDA) tools to generate designs with improved ability to withstand delay variations and process imperfections. By adopting a defect tolerance approach during the early stages of the design cycle, we introduce defect- awareness to Electronic Design Automation (EDA) tools for synthesizing robust netlists that can withstand delays induced by manufacturing defects and process imperfections. These defect tolerant designs, which are generated using a modified design (RTL2GDS) approach, have intelligently chosen timing buffers that can tolerate delay variations introduced during manufacturing, thereby introducing greater resilience to process variation and defectivity and ensuring correct circuit operation at the target design frequency. Furthermore, we present an evolutionary algorithm-based method to implement a multi-objective optimization of design goals, which improves robustness of the design while minimizing the impact on power, performance and area (PPA) of the design. This optimization method yields a pareto-optimal front for the designer to select among a set of robust designs that seamlessly integrates defect tolerance alongside PPA in the design space exploration, toward improving yield without compromising the target design characteristics.