Millimeter-wave Packaging Materials and CPW Interconnects on Silicon

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August 2022

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Abstract

Accurate millimeter wave (mm-wave) circuit and system design is challenging due to un- known dielectric properties above 40 GHz, higher loss due to multimode propagation in substrates, and electromagnetic modeling limitations when compared with on-wafer mea- surement. This dissertation attempts to address these challenges by studying material char- acterization techniques and coplanar waveguide (CPW) line performance on silicon wafers. The dielectric characterization techniques have been investigated from 10 MHz to 110 GHz for substrates and fixed thickness packaging dielectrics. Broadband data using a coaxial line technique was demonstrated for the first time in literature up to 67 GHz. The accuracy of the properties improves for material thicknesses which are greater than half wavelength. For the thin samples, a stacking technique has been introduced to electrically increase the thickness. The broadband data was achieved using a single 1.85 mm airline from 10 MHz to 67 GHz, followed by a WR10 waveguide from 75 to 110 GHz. As resonant techniques are more accu- rate, a microstrip ring resonator was used where the copper trace was printed using a craft cutter tool and was adhered onto non-copper clad materials. This is a fast, low-cost, and non-destructive solution and is suitable for frequencies below 20 GHz. This study will en- able high frequency design solutions for packaging technologies used for antennas-in-package (AiP) and three dimensional (3D) printed RF circuits. Next, broadband loss characterization of coplanar waveguide (CPW) transmission lines has been studied on undoped high resistivity silicon (HRS) from 10 MHz to 325 GHz. Electromagnetic (EM) modeling limi- tations in the Ansys HFSS simulation tool have been examined for full thickness wafers of 525μm and two innovative EM ports were introduced. The bridge-probe lumped port model showed promising results to address the probe parasitics at high frequency. The tunnel wave- port showed simulation capability up to 325 GHz which otherwise would be limited to 80 GHz using general waveport for 400 μm thick substrates. The on-wafer measurement data shows that unwrapped ground, narrow ground width and thinning of substrates can reduce the loss of the lines. A glass spacer was used to separate the wafer from the probe station chuck. Compared to simulation, higher loss was observed in the measured data up to 110 GHz due to a possible unavoidable parasitic surface channel in silicon. This problem can be mitigated by surface passivating the silicon. At frequencies from 140 to 325 GHz, this issue was not observed. The loss of the conventional CPW lines has been used as a baseline to characterize the performance of copper nanowire interconnect technology integrated within the lines. This work can contribute to the advancement of copper-to-copper interconnects for die-to-wafer or wafer-to-wafer connections for 3D packaging technology. The potential of HRS for passive device design was further explored by introducing short and open stubs on the center conductor of CPW lines as filter elements operating up to 325 GHz which showed excellent response compared with simulation.

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Engineering, Electronics and Electrical

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