Standard Cell Library Design with Transistor Folding Using 65nm Technology by Global Foundries

dc.contributor.advisorSechen, Carl M.
dc.creatorSalimath, Vibhav Kumarswami
dc.date.accessioned2018-08-13T18:32:57Z
dc.date.available2018-08-13T18:32:57Z
dc.date.created2018-05
dc.date.issued2018-05
dc.date.submittedMay 2018
dc.date.updated2018-08-13T18:32:59Z
dc.description.abstractWe use the concept of transistor folding to design some of the cells in the cell library. Transistor folding, also known as fingering of MOSFETs, is used when we require cells with larger drive strengths. By keeping the beta ratio (Wp / Wn) fixed, a greater number of transistors are arranged in parallel. Whenever there is a requirement of large current to the load, this technique of transistor folding is employed. The major advantage of using this technique is that it drastically reduces the resistances. To be more precise, if there are N transistors in parallel then the overall resistance reduces by a factor of N. Folding is used to optimize the resistance of the gate poly along the width of the transistor. Gate poly is driven from one end; hence, there is a reason to have a guideline that states maximum width of single finger. Folding is the only way to meet this guideline for large transistors. Our physical library has 16 functions, each with several drive sizes, giving a total of 83 cells. These 16 functions are comprised of simple functions as well as some complex functions. The complex functions were included in the library design because adding these complex functions improves the synthesis performance. Various parameters such as layout area, fall-time, rise-time, fall-transition time, and rise transition time are obtained during library characterization. The designed cells were characterized using Synopsys Siliconsmart ACE and we were able to automatically place and route various designs using Cadence Encounter. The static timing analysis was performed using Synopsys PrimeTime.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10735.1/5943
dc.language.isoen
dc.rights©2018 The Author. Digital access to this material is made possible by the Eugene McDermott Library. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
dc.subjectMetal oxide semiconductor field-effect transistors
dc.subjectApplication-specific integrated circuits
dc.subjectGate array circuits
dc.subjectLogic design
dc.subjectTiming circuits
dc.titleStandard Cell Library Design with Transistor Folding Using 65nm Technology by Global Foundries
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical Engineering
thesis.degree.grantorThe University of Texas at Dallas
thesis.degree.levelMasters
thesis.degree.nameMSEE

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