200-400 GHz Antennas in Integrated Circuits Incorporating Packaging Effects

There is an increasing demand for wider bandwidth in high data rate applications. Using frequency bands in the sub-millimeter wave and terahertz (THz) range allows for a significant improvement of fractional bandwidth. The rise in operational frequency translates to reduced wavelengths, which are comparable to the dimensions of the integrated circuits (ICs). This has made the integration of antennas on a chip or within a semiconductor package possible. Presented in this dissertation is a “simple” bond-wire antenna intended for operation at 180-GHz. At 178.3 GHz, a gold bond wire shaped in a half loop and terminated on a bond pad of a neighboring chip exhibits a measured peak gain of 2.5 dB at the 𝜙 = 90° plane. The antenna also exhibits > 20-GHz measured −10-dB |S11| bandwidth. These measured results compare favorably with the simulated results. This is the first bond-wire antenna (operating at 180-GHz) that can be used for wireless communication in the broadside direction (perpendicular to the IC). A 300-GHz on-chip patch antenna is also presented and the effects of semiconductor packaging on the antenna performance are explored. Full-wave simulations of the rectangular patch antenna, compliant with the metal stack and design rules of a 65-nm complementary metal– oxide–semiconductor (CMOS) process, are implemented. The simulated results show an increase of 13% in radiation efficiency, an increase of 1 dB in peak antenna gain, and a 7-GHz −10-dB |S11| bandwidth improvement, upon encapsulation within a quad-flat no-lead (QFN) package compared to one without encapsulation. Measured results (within a QFN package) of a 276-GHz CMOS signal generator with the same on-chip antenna, show ∼6 dB higher effective isotropic radiated power over that of an unpackaged chip, corroborating the simulation results. A technique to improve the efficiency, gain and impedance bandwidth of on-chip planar patch antennas, using the encapsulation material, is thus presented and design guidelines are suggested for future planar on-chip antenna implementation. An E-shaped patch geometry is simulated to demonstrate the improvement of impedance bandwidth and gain over a rectangular patch. The −10-dB |S11| bandwidth of 3 GHz for rectangular patch at 300 GHz, is improved four-fold to 12 GHz with this geometry. The peak gain also improves by ~1 dB. To further improve the gain of a rectangular patch antenna, a 420- GHz, eight-element on-chip series-fed patch antenna array is developed. This is the first array in this configuration to be implemented on chip. The measured gain at boresight matches the simulated gain of ~9 dB at 415.5 GHz. The overlapping measured and simulated radiation patterns of this antenna demonstrates the reliability of antenna designs using EM simulations at sub-millimeter wave and THz frequencies. Power input to on-chip antennas at 200-400 GHz cannot be accurately measured in the presence of probes. Preliminary simulation results presented show that root mean square voltage detectors along with a phase detector can be used to determine the antenna input impedance in-situ, thereby eliminating the use of probes for antenna measurements. The feasibility of this technique for determination of the antenna characteristics is documented.