High-Density On-Chip DC-DC Power Conversion: Architecture, Control Scheme, and Circuit Design



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Modern mobile devices have been developed with the trend towards improving performance, integrating further multiple functions in limited form factor, and providing long runtime. Therefore, high-density power converters are required to facilitate this trend, while maintaining fundamental features, such as high efficiency over the wide-load-range, fixed switching frequency, low EMI noise, high reliability, low latency, low-quiescent power consumption, and wide input voltage (VIN) for direct usage of the varied battery voltage. This dissertation describes advanced system architectures, control schemes, and circuit designs, which can overcome the design challenges to enhance power density of the DC-DC converters. First, the dissertation discusses achieving system-level miniaturization by improving the power distribution plan in the battery-operated mobile applications. To mitigate the design challenges, a 3-level converter is essential due to its half VIN swing, which allows direct supply connection with the varied battery voltage while using the thin-oxide devices, enabling power converter integration with another functional device on the same chip. Although the half VIN swing in the 3-level converter allows operating at high switching frequency, which induces small passives and fast response, the efficiency as well as VIN range reported in the published works was limited. To further improve the efficiency, a 20MHz all-NMOS 3-level converter is presented. To handle all-NMOS power switches even with varied VIN supply, such as battery, the isolated bootstrap circuit is proposed to mitigate the voltage charging issue in the 3-level high-side gate driving. Also, proposed is a precise sub-ns dead-time controller, which is integrated in the gate buffer stage, minimizing the dead-time power loss without sacrificing reliability. To deliver high power with tremendous current slew rate required in the mobile application processors, a 25 MHz, 4-phase power converter is presented. The converter employs a synchronized adaptive window hysteretic control to facilitate ultra-fast transient response and minimize output voltage (VO) undershoot and overshoot. Its inherent clock synchronization ability ensures current balancing among the phase sub-converters. The control is also capable of providing a wide range of programmable VO for dynamic voltage scaling, thereby efficiently saving system power. As the all-phase operation degrades the light-load efficiency, a 1-Cycle active phase count scheme is introduced to maintain high efficiency over a wide load range without degrading transient speed. To further integrate required design features for mobile applications, the hybrid digital-assisted double adaptive bound (DAB) converter is developed. The analog DAB controller achieves fast transient response, fixed switching frequency, high output regulation, and wide VIN supply in a compact structure. Combining the DAB control with a digital mode manager, the proposed hybrid converter provides four operation modes to further improve transient performance and wide-load range efficiency. Due to the single control loop assisted by the digital mode manager, the converter successfully utilizes fast and seamless mode transitions without any supply glitch.



DC-to-DC converters, Mobile apps, Power electronics