Thermal-aware Placement and High Level Synthesis for Hardware Security

dc.contributor.advisorSechen, Carl
dc.contributor.advisorCarrion Schafer, Benjamin
dc.creatorHu, Bo
dc.date.accessioned2022-07-27T14:29:20Z
dc.date.available2022-07-27T14:29:20Z
dc.date.created2021-05
dc.date.issued2021-04-23
dc.date.submittedMay 2021
dc.date.updated2022-07-27T14:29:21Z
dc.description.abstractShrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable Field Programmable Gate Arrays (FPGAs),coarse-grained runtime reconfigurable architectures (CGRRAs) and application-specific integrated circuits (ASICs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). This dissertation deals with this problem and provide a reliability-aware floorplanner which is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs) and seeks to extend their mean time to failure (MTTF) by balancing the usage of processing elements (PEs). The proposed method is based on a Mixed Integer Linear Programming (MILP) formulation, the solution to which produces appropriately-balanced mappings of workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime degradation. We first use this as the basis of a design space explorer that generates a variety of configurations, trading off PE displacement vs. MTTF. Then, an efficient and optimized mixed LP and ILP (MILP)-based aging-aware floorplanner is proposed to increase the MTTF without performance degradation. We also propose an integer linear programming (ILP)-based thermal-aware placement refinement algorithm that can be appended to any commercial placement and routing tool to decrease the maximum power density by an order of magnitude and appreciably reduce the peak temperature of an ASIC. Another aspect of hardware reliability is hardware obfuscation. The protection of intellectual property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavioral description for high-level synthesis (HLS) to a high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only the end-user has access to the full functionality of the chip. In all cases, the Time-ToBreak (T T B) is so long (at least 8 million hours) that for all practical purposes the designs are secure, while incurring area overheads of around 5%.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://hdl.handle.net/10735.1/9428
dc.language.isoen
dc.subjectTemperature control
dc.subjectTemperature measurements
dc.subjectComputer security
dc.subjectApplication-specific integrated circuits ǂx Thermal properties
dc.titleThermal-aware Placement and High Level Synthesis for Hardware Security
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical Engineering
thesis.degree.grantorThe University of Texas at Dallas
thesis.degree.levelDoctoral
thesis.degree.namePHD

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